
High-Side, Current-Sense Amplifiers with
12-Bit ADC and Op Amp/Comparator
MAX9611/MAX9612
14 _____________________________________________________________________________________
Slave Address
A bus master initiates communication with a slave
device by issuing a START (S) condition followed by a
slave address. When idle, the MAX9611/MAX9612 con-
tinuously wait for a START condition followed by their
slave address. When the MAX9611/MAX9612 recognize
a slave address, it is ready to accept or send data. The
MAX9611/MAX9612 offer 16 different slave addresses
using two address inputs, A1 and A0. See Table 2 for
different slave address options. The least significant bit
(LSB) of the address byte (R/W) determines whether
the master is writing to or reading from the MAX9611/
MAX9612 (R/W = 0 selects a write condition, R/W = 1
selects a read condition). After receiving the address,
the MAX9611/MAX9612 (slave) issue an acknowledge
by pulling SDA low for one clock cycle.
I2C Write Operation
A write operation (Figure 1) begins with the bus master
issuing a START condition followed by seven address
bits and a write bit (R/W = 0). If the address byte is
successfully received, the MAX9611/MAX9612 (slave)
issue an acknowledge (A). The master then writes to
the slave and the sequence is terminated by a STOP (P)
condition for a single write operation.
For a burst write operation, more data bytes are sent after
the register address before the transaction is terminated.
I2C Read Operation
In an I2C read operation (Figure 2), the bus master
issues a write command first by initiating a START condi-
tion followed by seven address bits, a write bit (R/W = 0)
and the 8-bit register address. The master then issues
a Repeated START (Sr) condition, followed by seven
address bits, a read bit (R/W = 1). If the address byte
is successfully received, the MAX9611/MAX9612 (slave)
issue an acknowledge (A). The master then reads from
the slave. For continuous read, the master issues an
acknowledge bit (AM) after each received byte. The
master terminates the read operation by sending a not
acknowledge (NA) bit. The MAX9611/MAX9612 then
release the data line SDA allowing the master to gener-
ate a STOP condition.
Table 2. MAX9611/MAX9612 Address
Description
Figure 1. I2C Write Operation
Figure 2. I2C Read Operation
A1
A0
DEVICE WRITE
ADDRESS (hex)
DEVICE READ
ADDRESS (hex)
0
0xE0
0xE1
0
1/3 x VCC
0xE2
0xE3
0
2/3 x VCC
0xE4
0xE5
0
VCC
0xE6
0xE7
1/3 x VCC
0
0xE8
0xE9
1/3 x VCC 1/3 x VCC
0xEA
0xEB
1/3 x VCC 2/3 x VCC
0xEC
0xED
1/3 x VCC
VCC
0xEE
0xEF
2/3 x VCC
0
0xF0
0xF1
2/3 x VCC 1/3 x VCC
0xF2
0xF3
2/3 x VCC 2/3 x VCC
0xF4
0xF5
2/3 x VCC
VCC
0xF6
0xF7
VCC
0
0xF8
0xF9
VCC
1/3 x VCC
0xFA
0xFB
VCC
2/3 x VCC
0xFC
0xFD
VCC
0xFE
0xFF
SINGLE WRITE
BURST WRITE
REGISTER ADDRESS
SLAVE ADDRESS
S0 A
AP
DATA
AA P
ACKNOWLEDGE FROM
MAX9611/MAX9612
R/W
STOP
REGISTER ADDRESS
SLAVE ADDRESS
S0 A
DATA 2
DATA 1
AA
DATA N
DATA 3
AA
ACKNOWLEDGE FROM
MAX9611/MAX9612
R/W
STOP
ACKNOWLEDGE FROM
MAX9611/MAX9612
ACKNOWLEDGE FROM
FROM MASTER
SINGLE READ
REGISTER ADDRESS
SLAVE ADDRESS
DATA
S
ASr1
R/W
0A
NO READ-ACKNOWLEDGE
FROM MASTER
R/W
AAMP
ACKNOWLEDGE FROM
MAX9611/MAX9612
BURST READ
REPEAT
START
REGISTER ADDRESS
SLAVE ADDRESS
DATA
S
ASr1
R/W
0A
R/W
A
DATA N
AM
NA P
AM
DATA