参数资料
型号: MAX9691EUA+T
厂商: Maxim Integrated Products
文件页数: 10/12页
文件大小: 0K
描述: IC COMPARATOR W/LE 8-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 带锁销
元件数: 1
输出类型: 补充型,ECL
电压 - 输入偏移(最小值): 6.5mV @ 5V
电流 - 输入偏压(最小值): 20µA @ 5V
电流 - 输出(标准): 50mA
电流 - 静态(最大值): 26mA
CMRR, PSRR(标准): 80dB CMRR,60dB PSRR
传输延迟(最大): 1.8ns
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
安装类型: 表面贴装
包装: 带卷 (TR)
MAX9691/MAX9692/MAX9693
The timing diagram (Figure 3) illustrates the series of
events that complete the compare function, under
worst-case conditions. The top line of the diagram illus-
trates two latch-enable pulses. Each pulse is high for
the compare function and low for the latch function. The
first pulse demonstrates the compare function; part of
the input action takes place during the compare mode.
The second pulse demonstrates a compare function
interval during which there is no change in the input.
The leading edge of the input signal (illustrated as a
large-amplitude, small-overdrive pulse) switches the
comparator after time interval tpd. Output Q and Q tran-
sistors are similar in timing. The input signal must occur
at time ts before the latch falling edge, and must be
maintained for time th after the edge to be acquired.
After th, the output is no longer affected by the input sta-
tus until the latch is again strobed. A minimum latch
pulse width of tpw(LE) is needed for the strobe opera-
tion, and the output transitions occur after a time tLE(±).
The MAX9691/MAX9692/MAX9693 will not false trip
(i.e., output invert) if one of the inputs is in the valid
common-mode range while the other input is outside
the common-mode range.
LATCH
ENABLE
DIFFERENTIAL
INPUT
VOLTAGE
Q
LATCH
COMPARE
ts
th
VOD
VIN
tLE(+)
VOS
50%
tpw(LE)
tpd
Figure 3. Timing Diagram
Single/Dual, Ultra-Fast, ECL-Output
Comparators with Latch Enable
_______________________________________________________________________________________
7
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