参数资料
型号: MAX97002EWP+T
厂商: Maxim Integrated Products
文件页数: 25/37页
文件大小: 0K
描述: IC AUDIO SUBSYSTEM 20WLP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: DirectDrive®
类型: D 类
输出类型: 1-通道(单声道),带立体声耳机
在某负载时最大输出功率 x 通道数量: 920mW x 1 @ 8 欧姆; 37mW x 2 @ 16 欧姆
电源电压: 2.7 V ~ 5.5 V
特点: 消除爆音,差分输入,I²C,静音,关闭,音量控制
安装类型: 表面贴装
供应商设备封装: 20-WLP
封装/外壳: 20-WFBGA,WLBGA
包装: 标准包装
其它名称: MAX97002EWP+TDKR
Audio Subsystem with Mono Class D
Speaker and Class H Headphone Amplifiers
MAX97002
31
Early STOP Conditions
The MAX97002 recognizes a STOP (P) condition at any
point during data transmission except if the STOP condi-
tion occurs in the same high pulse as a START (S) condi-
tion. For proper operation, do not send a STOP condition
during the same SCL high pulse as the START condition.
Slave Address
The slave address is defined as the seven most sig-
nificant bits (MSBs) followed by the read/write bit. For
the MAX97002 the 7 MSBs are 1001101. Setting the
read/write bit to 1 (slave address = 0x9B) configures the
MAX97002 for read mode. Setting the read/write bit to 0
(slave address = 0x9A) configures the MAX97002 for write
mode. The address is the first byte of information sent to
the MAX97002 after the START condition.
Acknowledge
The acknowledge bit (ACK) is a clocked 9th bit that
the MAX97002 uses to handshake receipt each byte
of data when in write mode (Figure 9). The MAX97002
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully received.
Monitoring ACK allows for detection of unsuccessful
data transfers. An unsuccessful data transfer occurs
if a receiving device is busy or if a system fault has
occurred. In the event of an unsuccessful data transfer,
the bus master retries communication. The master pulls
down SDA during the 9th clock cycle to acknowledge
receipt of data when the MAX97002 is in read mode. An
acknowledge is sent by the master after each read byte
to allow data transfer to continue. A not-acknowledge is
sent when the master reads the final byte of data from
the MAX97002, followed by a STOP condition.
Write Data Format
A write to the MAX97002 includes transmission of a
START condition, the slave address with the R/W bit set
to 0, one byte of data to configure the internal register
address pointer, one or more bytes of data, and a STOP
condition. Figure 10 illustrates the proper frame format
for writing one byte of data to the MAX97002. Figure 11
illustrates the frame format for writing n-bytes of data to
the MAX97002.
The slave address with the R/W bit set to 0 indicates that
the master intends to write data to the MAX97002. The
MAX97002 acknowledges receipt of the address byte
during the master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the MAX97002’s internal register address pointer. The
pointer tells the MAX97002 where to write the next byte
of data. An acknowledge pulse is sent by the MAX97002
upon receipt of the address pointer data.
The third byte sent to the MAX97002 contains the
data that is written to the chosen register. An acknowl-
edge pulse from the MAX97002 signals receipt of the
data byte. The address pointer autoincrements to the
next register address after each received data byte.
This autoincrement feature allows a master to write to
sequential registers within one continuous frame. The
master signals the end of transmission by issuing a
STOP condition. Register addresses greater than 0x09
are reserved. Do not write to these addresses.
Figure 9. Acknowledge
1
SCL
START
CONDITION
SDA
28
9
CLOCK PULSE FOR
ACKNOWLEDGMENT
ACKNOWLEDGE
NOT ACKNOWLEDGE
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