参数资料
型号: MAX9767ETJ+T
厂商: Maxim Integrated Products
文件页数: 11/33页
文件大小: 0K
描述: IC AMP AUDIO .75W STER AB 32TQFN
标准包装: 2,500
类型: AB 类
输出类型: 2 通道(立体声)
在某负载时最大输出功率 x 通道数量: 750mW x 2 @ 4 欧姆
电源电压: 2.7 V ~ 5.5 V
特点: 消除爆音,麦克风,静音,短路保护和热保护,关机
安装类型: 表面贴装
供应商设备封装: 32-TQFN-EP(5x5)
封装/外壳: 32-WFQFN 裸露焊盘
包装: 带卷 (TR)
MAX9765/MAX9766/MAX9767
750mW Audio Amplifiers with Headphone Amp,
Microphone Preamp, and Input Mux
______________________________________________________________________________________
19
condition, the bus remains active. When a STOP con-
dition or incorrect address is detected, the
MAX9765/MAX9766 internally disconnects SCL from
the serial interface until the next START condition, mini-
mizing digital noise and feedthrough.
Early STOP Conditions
The MAX9765/MAX9766 recognize a STOP condition at
any point during the transmission except if a STOP con-
dition occurs in the same high pulse as a START condi-
tion (Figure 5). This condition is not a legal I2C format;
at least one clock pulse must separate any START and
STOP conditions.
REPEATED START Conditions
A REPEATED START (Sr) condition may indicate a
change of data direction on the bus. Such a change
occurs when a command word is required to initiate a
read operation. Sr may also be used when the bus
master is writing to several I2C devices and does not
want to relinquish control of the bus. The MAX9765/
MAX9766 serial interface supports continuous write
operations with or without an Sr condition separating
them. Continuous read operations require Sr conditions
because of the change in direction of data flow.
Acknowledge Bit (ACK)
The acknowledge bit (ACK) is the ninth bit attached to
any 8-bit data word. The receiving device always gen-
erates ACK. The MAX9765/MAX9766 generate an ACK
when receiving an address or data by pulling SDA low
during the ninth clock period. When transmitting data,
the MAX9765/MAX9766 wait for the receiving device to
generate an ACK. Monitoring ACK allows for detection
of unsuccessful data transfers. An unsuccessful data
transfer occurs if a receiving device is busy or if a sys-
tem fault has occurred. In the event of an unsuccessful
data transfer, the bus master should reattempt commu-
nication at a later time.
Slave Address
The bus master initiates communication with a slave
device by issuing a START condition followed by a 7-bit
slave address (Figure 6). When idle, the MAX9765/
MAX9766 wait for a START condition followed by its
slave address. The serial interface compares each
address value bit-by-bit, allowing the interface to power
down immediately if an incorrect address is detected.
The LSB of the address word is the Read/Write (R/W)
bit. R/W indicates whether the master is writing to or
reading from the MAX9765/MAX9766 (R/W = 0 selects
the write condition, R/W = 1 selects the read condition).
After receiving the proper address, the MAX9765/
MAX9766 issue an ACK by pulling SDA low for one
clock cycle.
The MAX9765 has a factory/user-programmed address
(Table 2). The MAX9766 has a factory-programmed
address: 1001011.
SCL
SDA
START
CONDITION
STOP
CONDITION
REPEATED
START
CONDITION
START
CONDITION
tHD, STA
tSP
tBUF
tSU, STO
tLOW
tSU, DAT
tHD, DAT
tHIGH
tR
tF
Figure 3. 2-Wire Serial Interface Timing Diagram
SCL
SDA
SSr
P
Figure 4. START/STOP Conditions
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