参数资料
型号: MAX977ESD+
厂商: Maxim Integrated Products
文件页数: 4/17页
文件大小: 0K
描述: IC COMPARATOR DUAL 14-SOIC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
类型: 通用
元件数: 2
输出类型: CMOS,满摆幅,TTL
电压 - 电源,单路/双路(±): 2.7 V ~ 5.25 V
电压 - 输入偏移(最小值): 2mV @ 5V
电流 - 输入偏压(最小值): 0.1µA @ 5.25V
电流 - 静态(最大值): 500µA
CMRR, PSRR(标准): 90dB CMRR,90dB PSRR
传输延迟(最大): 820ns
磁滞: 4mV
工作温度: -40°C ~ 85°C
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
安装类型: 表面贴装
包装: 管件
产品目录页面: 1386 (CN2011-ZH PDF)
MAX975/MAX977
powered up, the high-speed comparator is enabled,
the low-power comparator is disabled, and STAT goes
high, placing the MAX975 back into high-speed mode
(Figure 2).
Use an external capacitor, CSTO, to program the timeout
period required for the comparator to enter auto-
standby mode. Determine the capacitor required for a
particular timeout period by the relationship tASB =
10 x Cs, where C is in pF. For example, connecting a
0.1F capacitor to STO_ results in a timeout period of
1sec. The propagation delay of OUT_ when exiting auto
standby mode is equivalent to the low - power-mode
propagation delay. When STAT_ goes low, the low-
power comparator is disabled and the high-speed com-
parator is ready for operation. To bring the comparator
out of auto-standby mode without a transition occurring
on OUT_, toggle LP low-high-low. The LP pin is sensitive
to noise. If fall times larger than 10s are expected,
bypass LP with a 0.1F capacitor to GND. To disable
auto-standby mode, drive STO_ low or connect it to
ground. Note that driving STO_ low while in auto-
standby mode will not bring the comparator out of auto-
standby mode. Also, if driving STO_ with an open drain,
leakage must be less than 1nA. On power-up, the
device is in high-speed mode unless LP is high. The
MAX977 operates in the same manner as the MAX975.
Low-Power Mode
Driving LP high switches the MAX975/MAX977 to low-
power mode. In this mode, the supply current drops to
a maximum of 5
A, and propagation delay increases
typically to 480ns. The high-speed comparator is dis-
abled and the low-power comparator is enabled for
continuous operation. Return to high-speed mode by
driving LP low. The LP pin is sensitive to noise. If fall
times larger than 10s are expected, bypass LP with a
0.1F capacitor to GND. The logic state and sink/
source capabilities of OUT_ remain unchanged in low-
power mode.
Input-Stage Circuitry
The MAX975/MAX977 input common-mode range is
from -0.2V to (VCC - 1.2V). But the voltage range for
each comparator input extends to both VCC and GND
rails. The output remains in the correct logic state while
one or both of the inputs are within the common-mode
range. If both input levels are out of the common-mode
range, input-stage current saturation occurs and the
output becomes unpredictable.
Single/Dual, +3V/+5V Dual-Speed
Comparators with Auto-Standby
12
______________________________________________________________________________________
tPWD
tASB
tASD
tPD-
tPD+
tLPSH
tASBE
tLPCD
tLPE
tHSE
VCC
VOL
VOH
VOS
DIFFERENTIAL
INPUT
VOLTAGE
OUT_
STAT_
ICC (TYP)
LP
0V
300
A
3
A
tASCD
VCC
A
Figure 2. Timing Diagram
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