参数资料
型号: MAX9860EVKIT+
厂商: Maxim Integrated Products
文件页数: 11/38页
文件大小: 0K
描述: KIT EVALUATION FOR MAX9860
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: *
MAX9860
16-Bit Mono Audio Voice Codec
19
Maxim Integrated
Digital Audio Interface
The MAX9860’s digital audio interface supports a wide
range of operating modes to ensure maximum compati-
bility. See Figures 1 through 4 for timing diagrams. In
master mode, the MAX9860 outputs LRCLK and BCLK,
while in slave mode, they are inputs. When operating in
master mode, BCLK can be configured in a number of
ways to ensure compatiblity with other audio devices.
Table 5. Digital Audio Interface Registers
REGISTER ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
0x06
MAS
WCI
DBCI
DDLY
HIZ
TDM
0
0x07
0
ABCI
ADLY
ST
BSEL
BITS
FUNCTION
MAS
Master Mode
0 = The MAX9860 operates in slave mode with LRCLK and BCLK configured as inputs.
1 = The MAX9860 operates in master mode with LRCLK and BCLK configured as outputs.
WCI
LRCLK Invert
0 = Left-channel data is input and output while LRCLK is low.
1 = Right-channel data is input and output while LRCLK is low.
WCI is ignored when TDM = 1.
DBCI
DAC BCLK Invert (must be set to ABCI)
In master and slave mode:
0 = SDIN is latched into the part on the rising edge of BCLK.
1 = SDIN is latched into the part on the falling edge of BCLK.
In master mode:
0 = LRCLK changes state following the rising edge of BCLK.
1 = LRCLK changes state following the falling edge of BCLK.
DDLY
DAC Delay Mode
0 = SDIN data is latched on the first BCLK edge following an LRCLK edge.
1 = SDIN data is assumed to be delayed one BCLK cycle so that it is latched on the 2nd BCLK edge
following an LRCLK edge (I2S-compatible mode).
DDLY is ignored when TDM = 1.
HIZ
SDOUT High-Impedance Mode
0 = SDOUT is set either high or low after all data bits have been transferred out of the part.
1 = SDOUT goes to a high-impedance state after all data bits have been transferred out of the part,
allowing SDOUT to be shared by other devices.
Use HIZ only when TDM = 1.
TDM
TDM Mode Select
0 = LRCLK signal polarity indicates left and right audio.
1 = LRCLK is a framing pulse which transitions polarity to indicate the start of a frame of audio data
consisting of multiple channels.
When operating in TDM mode the left channel is output immediately following the frame sync pulse. If right-
channel data is being transmitted, the 2nd channel of data immediately follows the 1st channel data.
ABCI
ADC BCLK Invert (must be set to DBCI)
0 = SDOUT is valid on the rising edge of BCLK and transitions immediately after the rising edge.
1 = SDOUT is valid on the falling edge of BCLK and transitions immediately after the falling edge.
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MAX9860EVKIT+ 功能描述:音频 IC 开发工具 MAX9860 Eval Kit RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V
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MAX9867ETJ+T 功能描述:接口—CODEC Stereo Audio CODEC for Portable Devices RoHS:否 制造商:Texas Instruments 类型: 分辨率: 转换速率:48 kSPs 接口类型:I2C ADC 数量:2 DAC 数量:4 工作电源电压:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:DSBGA-81 封装:Reel
MAX9867EVKIT+ 功能描述:音频 IC 开发工具 MAX9867 Eval Kit RoHS:否 制造商:Texas Instruments 产品:Evaluation Kits 类型:Audio Amplifiers 工具用于评估:TAS5614L 工作电源电压:12 V to 38 V
MAX9867EWV+ 制造商:Maxim Integrated Products 功能描述:LOW-POWER, STEREO AUDIO CODEC - Rail/Tube