参数资料
型号: MAX9867ETJ+
厂商: Maxim Integrated Products
文件页数: 4/55页
文件大小: 0K
描述: IC STEREO AUD CODEC LP 32TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 立体声音频
数据接口: I²C,串行
分辨率(位): 18 b
ADC / DAC 数量: 2 / 2
三角积分调变:
动态范围,标准 ADC / DAC (db): 85 / 90
电压 - 电源,模拟: 1.65 V ~ 1.95 V
电压 - 电源,数字: 1.65 V ~ 1.95 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 托盘
MAX9867
Ultra-Low Power Stereo Audio Codec
12
______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum BCLK High Time
tBCLKH
Slave operation
30
ns
Minimum BCLK Low Time
tBCLKL
Slave operation
30
ns
BCLK or LRCLK Rise and Fall
tR, tF
Master operation, CL = 15pF
7
ns
SDIN or LRCLK to BCLK Setup
Time
tSU
20
ns
SDIN or LRCLK to BCLK Hold
Time
tHD
0ns
SDOUT Delay Time from BCLK
Rising Edge
tDLY
CL = 30pF
0
40
ns
I
2C TIMING CHARACTERISTICS (VDVDD = 1.65V)
Serial-Clock Frequency
fSCL
0
400
kHz
Bus Free Time Between STOP
and START Conditions
tBUF
1.3
s
Hold Time (REPEATED) START
Condition
tHD, STA
0.6
s
SCL Pulse-Width Low
tLOW
1.3
s
SCL Pulse-Width High
tHIGH
0.6
s
Setup Time for a REPEATED
START Condition
tSU, STA
0.6
s
Data Hold Time
tHD, DAT
RPU, SDA = 475
0
900
ns
Data Setup Time
tSU, DAT
100
ns
SDA and SCL Receiving Rise
Time
tR
(Note 10)
20 +
0.1CB
300
ns
SDA and SCL Receiving Fall
Time
tF
(Note 10)
20 +
0.1CB
300
ns
SDA Transmitting Fall Time
tF
RPU, SDA = 475
(Note 10)
20 +
0.1CB
250
ns
Setup Time for STOP Condition
tSU, STO
0.6
s
Bus Capacitance
CB
400
pF
Pulse Width of Suppressed Spike
tSP
050
ns
Note 2: The MAX9867 is 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design.
Note 3: Clocking all zeros into the DAC, master mode, and differential headphone mode.
Note 4: DAC performance measured at the headphone outputs.
Note 5: Dynamic range measured using the EIAJ method. -60dBFS 1kHz output signal, A-weighted, and normalized to 0dBFS.
f = 20Hz to 20kHz.
Note 6: Performance measured using microphone inputs, unless otherwise stated.
Note 7: Performance measured using line inputs.
Note 8: Performance measured using DAC, unless otherwise stated. LRCLK = 8kHz, unless otherwise stated.
Note 9: In master-mode operation, the accuracy of the MCLK input proportionally determines the accuracy of the sample clock rate.
Note 10: CB is in pF.
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VPVDD = VDVDD = VDVDDIO = +1.8V, RL = ∞, headphone load (RL) connected between _OUTP and _OUTN in differential
mode, CREF = 2.2F, CMICBIAS = CPREG = CREG = 1F, AVPRE = +20dB, AVPGAM = 0dB, AVDAC = 0dB, AVLINE = +20dB, AVVOL =
0dB, MCLK = 13MHz, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
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