参数资料
型号: MAX9879ERV+
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 音频控制
英文描述: Stereo Class D Audio Subsystem with DirectDrive Headphone Amplifier; Package: UCSP (R);30 pin;6 mm² ; Temperature: -40°C to +85°C
中文描述: 2 CHANNEL(S), VOLUME CONTROL CIRCUIT, PBGA30
封装: 2.50 X 3 MM, 0.50 MM PITCH, ROHS COMPLAINT, UCSP-30
文件页数: 15/31页
文件大小: 539K
代理商: MAX9879ERV+
MAX9879
Stereo Class D Audio Subsystem
with DirectDrive Headphone Amplifier
22
______________________________________________________________________________________
I2C Register Description
Zero-Crossing Detection (ZCD)
Zero-crossing detection limits distortion in the output
signal during volume transitions by delaying the transi-
tion until the mixer output crosses the internal bias volt-
age. A timeout period (typically 60ms) forces the
volume transition if the mixer output signal does not
cross the bias voltage.
1 = Zero-crossing detection is enabled.
0 = Zero-crossing detection is disabled.
Differential Input Configuration (
ΔIN_)
The inputs INA_ and INB_ can be configured for mono
differential or stereo single-ended operation.
1 = IN_ is configured as a mono differential input with
IN_2 as the positive and IN_1 as the negative input.
0 = IN_ is configured as a stereo single-ended input
with IN_2 as the right and IN_1 as the left input.
Preamplifier Gain (PGAIN_)
The preamplifier gain of INA_ and INB_ can be pro-
grammed by writing to PGAIN_.
00 = 0dB
01 = +5.5dB
10 = +20dB
11 = Reserved
I2C Address
The slave address of the MAX9879 is 1001101R/(W)
(write: 0x9A, read: 0x9B).
Table 1. Register Map
REGISTER
ADDRESS
POR STATE
B7
B6
B5
B4
B3
B2
B1
B0
Input Mode
Control
0x00
0x40
0
ZCD
ΔINA
ΔINB
PGAINA
PGAINB
Speaker
Volume
Control
0x01
0x00
0
SPKVOL
Left
Headphone
Volume
Control
0x02
0x00
0
HPLVOL
Right
Headphone
Volume
Control
0x03
0x00
0
HPRVOL
Output Mode
Control
0x04
0x49
SHDN
BYPASS
0
ENB
ENA
LSPK
EN
RSPK
EN
HPEN
Table 2. Input Mode Control Register
REGISTER
B7
B6
B5
B4
B3
B2
B1
B0
0x00
0
ZCD
ΔINA
ΔINB
PGAINA
PGAINB
I2C Interface
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