参数资料
型号: MAX9930EVKIT+
厂商: Maxim Integrated
文件页数: 14/16页
文件大小: 0K
描述: KIT EVAL FOR MAX9930
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
类型: 对数探测器/控制器
频率: 2MHz ~ 1.6GHz
适用于相关产品: MAX9930
已供物品:
2MHz to 1.6GHz 45dB RF-Detecting
Controllers and RF Detector
Waveform Considerations
The MAX9930–MAX9933 family of logarithmic amplifiers
respond to voltage, not power, even though input levels
are specified in dBm. It is important to realize that input
Block Diagram
signals with identical RMS power but unique waveforms
result in different log amp outputs. Differing signal wave-
forms result in either an upward or downward shift in the
SHDN
V CC
OUTPUT-
ENABLE
DELAY
logarithmic intercept. However, the logarithmic slope
remains the same; it is possible to compensate for known
waveform shapes by baseband process.
It must also be noted that the output waveform is generat-
ed by first rectifying and then averaging the input signal.
RFIN
SET
LOG
DETECTOR
V-I*
g m
BLOCK
x1
BUFFER
OUT
This method should not be confused with RMS or peak-
detection methods.
MAX9930
MAX9931
C CLPF
MAX9932
Layout Considerations
As with any RF circuit, the layout of the MAX9930 –
MAX9933 circuits affects performance. Use a short 50 ?
GND
line at the input with multiple ground vias along the
SHDN
OUTPUT-
length of the line. The input capacitor and resistor
should both be placed as close as possible to the IC.
V CC should be bypassed as close as possible to the IC
with multiple vias connecting the capacitor to the
ground plane. It is recommended that good RF compo-
V CC
RFIN
LOG
DETECTOR
g m
BLOCK
ENABLE
DELAY
x1
OUT
nents be chosen for the desired operating frequency
range. Electrically isolate RF input from other pins
BUFFER
(especially SET) to maximize performance at high
frequencies (especially at the high power levels of
the MAX9932).
MAX9933
V-I*
C CLPF
GND
Chip Information
PROCESS: High-Frequency Bipolar
*INVERTING VOLTAGE TO CURRENT CONVERTER.
14
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