参数资料
型号: MAXQ2010-KIT#
厂商: Maxim Integrated
文件页数: 33/34页
文件大小: 0K
描述: EVALUATION KIT FOR MAX2010
标准包装: 1
类型: 微控制器
已供物品: 板,线缆,CD,文档,电源
MAXQ2010
16-Bit Mixed-Signal Microcontroller
with LCD Interface
8
_______________________________________________________________________________________
Note 12: Programming time does not include overhead associated with the utility ROM interface.
Note 13: VREF = VAVDD.
Note 14: The operational input voltage range for each individual input of a differentially configured pair is from GND to AVDD. The
operational input voltage difference is from -VREF/2 to +VREF/2.
Note 15: The typical value is applied when a conversion is requested with ADPMO = 0. Under these conditions, the minimum delay
is met. If ADPMO = 1, the user is responsible for ensuring the 4s delay time is met.
Note 16: Switching ADC reference from either internal or external reference to AVDD. Sample accuracy is not guaranteed prior to
ADC reference settlement.
Note 17: Total on-board decoupling capacitance on the AVDD pin < 100nF. The output impedance of the regulator driving the
AVDD pin < 10
Ω.
Note 18: This parameter is guaranteed by design and is not production tested.
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SPI (See Figures 1 and 2)
SPI Master Operating Frequency
1/tMCK
fCK/2
MHz
SPI Slave Operating Frequency
1/tSCK
fCK/8
MHz
SCLK Output Pulse-Width
High/Low
tMCH, tMCL
(tMCK/2)
- 25
ns
SCLK Input Pulse-Width
High/Low
tSCH, tSCL
tSCK/2
ns
MOSI Output Hold Time After
SCLK Sample Edge
tMOH
CL = 50pF
(tMCK/2)
- 25
ns
MOSI Output Valid to Sample
Edge
tMOV
(tMCK/2)
- 25
ns
MISO Input Valid to SCLK
Sample Edge Rise/Fall Setup
tMIS
25
ns
MISO Input to SCLK Sample
Edge Rise/Fall Hold
tMIH
0
ns
SCLK Inactive to MOSI Inactive
tMLH
(tMCK/2)
- 25
ns
SSEL Active to First Shift Edge
tSSE
4tCK
ns
MOSI Input to SCLK Sample
Edge Rise/Fall Setup
tSIS
20
ns
MOSI Input from SCLK Sample
Edge Transition Hold
tSIH
tCK +
25
ns
MISO Output Valid After SCLK
Shift Edge Transition
tSOV
3tCK +
25
ns
SSEL Inactive
tSSH
tCK +
25
ns
SCLK Inactive to SSEL Rising
tSD
tCK +
25
ns
MISO Output Disabled After
SSEL Edge Rise
tSLH
2tCK +
50
ns
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