参数资料
型号: MAXQ610J-0000+T
厂商: Maxim Integrated Products
文件页数: 16/29页
文件大小: 0K
描述: IC MCU 16BIT 64K IR MOD 44TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: MAXQ®
核心处理器: RISC
芯体尺寸: 16-位
速度: 12MHz
连通性: SPI,UART/USART
外围设备: 欠压检测/复位,红外线,电源故障,POR,WDT
输入/输出数: 32
程序存储器容量: 64KB(64K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 1.7 V ~ 3.6 V
振荡器型: 内部
工作温度: 0°C ~ 70°C
封装/外壳: 44-WFQFN 裸露焊盘
包装: 带卷 (TR)
其它名称: 90-M6800+AT3
MAXQ610
16-Bit Microcontroller with Infrared Module
______________________________________________________________________________________
23
If a reset is caused by a power-fail, the power-fail moni-
tor can be set to one of the following intervals:
Always on—continuous monitoring
211 nanopower ring oscillator clocks (~256ms)
212 nanopower ring oscillator clocks (~512ms)
213 nanopower ring oscillator clocks (~1.024s)
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
nanopower ring oscillator cycles. If VDD > VRST during
detection, VDD is monitored for an additional nanopow-
er ring oscillator period. If VDD remains above VRST for
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the
CPU exits the reset state in less than 20 crystal cycles
after the reset source is removed.
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
COMMENTS
A
On
Off
VDD < VPOR.
B
On
VPOR < VDD < VRST.
Crystal warmup time, tXTAL_RDY.
CPU held in reset.
C
On
VDD > VRST.
CPU normal operation.
D
On
Power drop too short.
Power-fail not detected.
E
On
VRST < VDD < VPFW.
PFI is set when VRST < VDD < VPFW and maintains
this state for at least tPFW, at which time a power-
fail interrupt is generated (if enabled).
CPU continues normal operation.
F
On
(Periodically)
Off
Yes
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
G
On
VDD > VRST.
Crystal warmup time, tXTAL_RDY.
CPU resumes normal operation from 8000h.
H
On
(Periodically)
Off
Yes
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor is turned on periodically.
I
Off
VDD < VPOR.
Device held in reset.
No operation allowed.
Table 4. Power-Fail Detection States During Normal Operation
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