参数资料
型号: MAXQ622-KIT#
厂商: Maxim Integrated Products
文件页数: 35/35页
文件大小: 0K
描述: EVALUATION KIT FOR MAXQ622
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
系列: MAXQ®
类型: MCU
适用于相关产品: MAXQ622
所含物品: 2 个板,线缆,CD
相关产品: MAXQ622X-0000+-ND - IC MCU 16BIT IR MOD BARE DIE
MAXQ622G-0000+-ND - IC MCU 16BIT 128KB IR MOD 64LQFP
其它名称: 90-M6900#KIT
9
Maxim Integrated
16-Bit Microcontrollers with
Infrared Module and Optional USB
MAXQ612/MAXQ622
I2C BUS CONTROLLER TIMING
(Notes 6, 21) (Figure 2)
Note 1: Specifications to 0NC are guaranteed by design and are not production tested.
Note 2: VPFW can be programmed to the following nominal voltage trip points: 1.8V, 1.9V, 2.55V, and 2.75V Q3%. The values
listed in the Recommended Operating Conditions table are for the default configuration of 1.8V nominal.
Note 3: It is not recommended to write to flash when the supply voltage drops below the power-fail warning levels, as there is
uncertainty in the duration of continuous power supply. The user application should check the status of the power-fail
warning flag before writing to flash to ensure complete write operations.
Note 4: The power-fail warning monitor and the power-fail reset monitor are designed to track each other with a minimum delta
between the two of 0.11V.
Note 5: The power-fail reset and POR detectors are designed to operate in tandem to ensure that one or both of these signals
is active at all times when VDD < VRST, ensuring the device maintains the reset state until minimum operating voltage is
achieved.
Note 6: Guaranteed by design and not production tested.
Note 7: IS1 is measured with the USB data RAM powered down.
Note 8: The power-check interval (PCI) can be set to always on, or to 1024, 2048, or 4096 nanopower ring clock cycles.
Note 9: Measured on the VDD pin and the device not in reset. All inputs are connected to GND or VDD. Outputs do not source/
sink any current. The device is executing code from flash memory.
Note 10: Current consumption during POR when powering up while VDD is less than the POR release voltage.
Note 11: The minimum amount of time that VDD must be below VPFW before a power-fail event is detected.
Note 12: The maximum total current, IOH(MAX) and IOL(MAX), for all listed outputs combined should not exceed 25mA to satisfy the
maximum specified voltage drop. This does not include the IRTX output.
Note 13: External clock frequency must be 12MHz to support USB functionality. Full-speed USB(12Mbps)-required bit-rate accu-
racy is Q2500ppm or Q0.25%. This is inclusive of all potential error sources: frequency tolerance, temperature, aging,
crystal capacitive loading, board layout, etc.
Note 14: Programming time does not include overhead associated with utility ROM interface.
PARAMETER
SYMBOL
STANDARD MODE
FAST MODE
UNITS
MIN
MAX
MIN
MAX
I2C Bus Operating Frequency
fI2C
0
100
0
400
kHz
System Frequency
fSYS
0.90
3.60
MHz
I2C Bit Rate
fI2C
fSYS/8
Hz
Hold Time After (Repeated) START
tHD:STA
4.0
0.6
F
s
Clock Low Period
tLOW_I2C
4.7
1.3
F
s
Clock High Period
tHIGH_I2C
4.0
0.6
F
s
Setup Time for Repeated START
tSU:STA
4.7
0.6
F
s
Hold Time for Data (Notes 22, 23)
tHD:DAT
0
3.45
0
0.9
F
s
Setup Time for Data (Note 24)
tSU:DAT
250
100
ns
SDA/SCL Fall Time (Note 20)
tF_I2C
300
20 + 0.1CB
300
ns
SDA/SCL Rise Time (Note 20)
tR_I2C
1000
20 + 0.1CB
300
ns
Setup Time for STOP
tSU:STO
4.0
0.6
F
s
Bus Free Time Between STOP and
START
tBUF
4.7
1.3
F
s
Capacitive Load for Each Bus Line
CB
400
pF
Noise Margin at the Low Level for
Each Connected Device (Including
Hysteresis)
VnL_I2C
0.1 x VDD
V
Noise Margin at the Low Level for
Each Connected Device (Including
Hysteresis)
VnH_I2C
0.2 x VDD
V
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