参数资料
型号: MAXQ7670ATL+T
厂商: Maxim Integrated Products
文件页数: 18/38页
文件大小: 0K
描述: IC MCU W/10BIT ADC 40TQFN-EP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: MAXQ®
核心处理器: RISC
芯体尺寸: 16-位
速度: 16MHz
连通性: CAN,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 7
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 16
电压 - 电源 (Vcc/Vdd): 2.25 V ~ 3.6 V
数据转换器: A/D 8x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 40-WFQFN 裸露焊盘
包装: 带卷 (TR)
MAXQ7670
Microcontroller with 10-Bit ADC,
PGA, 64KB Flash, and CAN Interface
______________________________________________________________________________________
25
frequency is limited to SYSCLK/2 in master mode and
SYSCLK/8 in slave mode. Figure 10 shows the function-
al diagram of the SPI port. Figures 1 and 2 illustrate the
timing parameters listed in the
Electrical Characteristics
table.
General-Purpose Digital I/Os
The MAXQ7670 provides seven general-purpose digital
I/Os (GPIOs). Some of the GPIOs include an additional
special function (SF), such as a timer input/output. For
example, the state of P0.6/T0 is programmable to
depend on timer channel 0 logic. When used as a port,
each I/O is configurable for high-impedance, weak
pullup to DVDDIO or pulldown to GNDIO. At power-up,
each GPIO is configured as an input with a pullup to
DVDDIO. In addition, each GPIO can be programmed
to cause an interrupt (on falling or rising edges). In stop
mode, use any interrupt to wake-up the device.
The port direction (PD) register determines the
input/output direction of each I/O. The port output (PO)
register contains the current state of the logic output
buffers. When an I/O is configured as an output, writing
to the PO register controls the output logic state.
Reading the PO register shows the current state of the
output buffers, independent of the data direction. The
port input (PI) register is a read-only register that
always reflects the logic state of the I/Os.
SFR DATA BUS
READ BUFFER
SHIFT REGISTER
LSB(0)
MSB (15)
MISO
MASTER
SLAVE
SPI CONTROL UNIT
SYSCLK
SPI INTERRUPT
/2 MASTER (MAX)
/8 SLAVE (MAX)
SHIFT CLK
0
7
SPI CONTRL REG (SPICN)
SPI CONTRL REG (SPICF)
SPI CONTRL REG (SPICK)
MASTER/SLAVE SELECT
SCLK OUT
SCLK IN
SPI ENABLE
MASTER
MOSI
SCLK
DVDDIO
SLAVE
MASTER
MAXQ7670
SS
Figure 10. SPI Functional Diagram
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