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参数资料
| 型号： | MAXQ8913EWG+T |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 10 MHz, RISC MICROCONTROLLER, PBGA58 |
| 封装： | ROHS COMPLIANT, WLP-58 |
| 文件页数： | 19/22页 |
| 文件大小： | 281K |
| 代理商： | MAXQ8913EWG+T |
MAXQ8913
16-Bit, Mixed-Signal Microcontroller with Op Amps,
ADC, and DACs for All-in-One Servo Loop Control
6
_______________________________________________________________________________________
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDVDD = VAVDD = 2.7V to 3.6V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Last Sample Edge to MOSI
Output Change (MOSI Last Hold)
tMLH
tMCK/
2 - tRF
ns
MISO Input Valid to SCLK
Sample Edge (MISO Setup)
tMIS
(Note 13)
2tRF
ns
MISO Input Hold After SCLK
Sample Edge
tMIH
0
ns
SPI: SLAVE MODE (See Figures 1, 3)
SPI Slave Operating Frequency
1/tSCK
fSYS/4
kHz
SCLK Input Pulse-Width
High/Low
tSCH, tSCL
tSCK/
2 - tRF
ns
I/O Rise/Fall Time
(This parameter is device
dependent.)
tRF
CL = 15pF, pullup = 560
16
ns
SSEL Active to First Shift Edge
tSSE
tRF
ns
MOSI Input to SCLK Sample
Edge Rise/Fall Setup
tSIS
tRF
ns
MOSI Input from SCLK Sample
Edge Transition Hold
tSIH
tRF
ns
MISO Output Valid After SCLK
Shift Edge Transition
tSOV
(Note 13)
2tRF
ns
SSEL Inactive to Next SSEL
Asserted
tSSH
tSYS +
tRF
ns
SCLK Inactive to SSEL
Deasserted
tSD
tRF
ns
MISO Output Disabled After
SSEL Edge Deasserted
tSLH
2tSYS
+ 2tRF
ns
Note 1:
Specifications to -20°C are guaranteed by design and are not production tested.
Note 2:
Connect to ground through a 1F capacitor.
Note 3:
Crystal connected to HFXIN, HFXOUT. Operating in /1 mode. Measured on the DVDD pin and the device not in reset. All
inputs are connected to GND or DVDD. Outputs do not source/sink any current. One timer B enabled, with the device exe-
cuting code from flash.
Note 4:
ISTOP is the total current into the device when the device is in stop mode.
Note 5:
Regulator, brownout disabled. Stop mode current through AVDD and DVDD.
Note 6:
Regulator disabled, brownout enabled. Stop mode current through AVDD and DVDD.
Note 7:
Regulator enabled, brownout enabled.
Note 8:
IOH(MAX) + IOL(MAX) for all outputs combined should not exceed 35mA to meet the specification.
Note 9:
VREF = VAVDD.
Note 10: The operational input voltage range for each individual input of a differentially configured pair is from GND to AVDD. The
operational input voltage difference is from -VREF/2 to +VREF/2.
Note 11: The typical value is applied when a conversion is requested with ADPMO = 0. Under these conditions, the minimum delay
is met. If ADPMO = 1, the user is responsible for ensuring the 4s delay time is met.
Note 12: Total on-board decoupling capacitance on the AVDD pin < 100nF. The output impedance of the regulator driving the
AVDD pin < 10
Ω.
Note 13: This value is the sum of input R/F and output R/F.
Note 14: Guaranteed by design and characterization.
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