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参数资料
| 型号： | MB86291APFVS |
| 厂商： | FUJITSU LTD |
| 元件分类： | 图形处理器 |
| 英文描述： | Graphics Display Controller |
| 中文描述： | GRAPHICS PROCESSOR, PQFP208 |
| 封装： | 0.50 MM PITCH, PLASTIC, QFP-208 |
| 文件页数： | 5/25页 |
| 文件大小： | 243K |
| 代理商： | MB86291APFVS |
MB86291A
5
Host Interface Pins
Pin Name
Note : The host interface can connect the MB86291A to the SH4 (SH7750) or SH3 (SH7709) from Hitachi Ltd.
the V832 from NEC, or to the SPARClite (MB86833) from Fujitsu without any external circuit in between.
(Using the SRAM interface allows the MB86291A to use another CPU.) The host CPU is set by the
MODE0 and MODE1 pins as shown below.
Note : The MODE2 pin can be used to set the Ready signal level to be used upon completion of the bus cycle. To
use the MODE2 signal at "H" level, set the software setting to two cycles.
Input/output
Function
MODE0 to MODE2
Input
Host CPU mode/Ready mode select
RESET
Input
Hardware reset
D0 to D31
Input/output
Host CPU bus data
A2 to A24
Input
Host CPU bus address (Connect A[24] to MWR in V832 mode.)
BCLKI
Input
Host CPU bus clock
BS
Input
Bus cycle start signal
CS
Input
Chip select signal
RD
Input
Read strobe signal
WE0
Input
D0 to D7 write strobe signal
WE1
Input
D8 to D15 write strobe signal
WE2
Input
D16 to D23 write strobe signal
WE3
Input
D24 to D31 write strobe signal
RDY
Output
Tristate
Wait request signal
(“0” for wait state with SH3; “1” for wait state with SH4, V832, or SPARClite)
DREQ
Output
DMA request signal (active low with both SH and V832)
DRACK/DMAAK
Input
DMA request acknowledge signal (Connect this to DMAAK in V832 mode.
Active high with both SH and V832.)
DTACK/TC
Input
DMA transfer strobe signal (Connect this to TC in V832 mode. SH = active
high, V832 = active low)
INT
Output
Host CPU interrupt signal (SH = active low, V832 = active high)
TEST0, TEST1,
TESTH0 to TESTH5
Input
Test signal
MODE1 pin
MODE0 pin
CPU Type
L
L
SH3
L
H
SH4
H
L
V832
H
H
SPARClite
MODE2 pin
Ready signal mode
L
Set RDY signal to "Not Ready" level upon completion of bus cycle.
H
Set RDY signal to "Ready" level upon completion of bus cycle.
相关PDF资料 |
PDF描述 |
|---|---|
| MB86292 | Graphics Display Controller |
| MB86292PFFS-G-BND | Graphics Display Controller |
| MB86293 | Grraphiics Conttrrollllerr Speciiffiicattiions |
| MB86294 | Grraphiics Controller specifications |
| MB86294S | Grraphiics Controller specifications |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86291APFVS-G-BND-DLE1 | 制造商:FUJITSU 功能描述:CONTROLLER GRAPHDISPLAY QFP208 |
| MB86291APFVSGBNDL | 制造商:Fujitsu 功能描述: |
| MB86291APVSR-G-BND-DLE1 | 制造商:FUJITSU 功能描述: |
| MB86291ASPVSR-G-BND-DLE1 | 制造商:FUJITSU 功能描述: |
| MB86292 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Graphics Display Controller |
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