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参数资料
| 型号： | MB86292PFFS-G-BND |
| 厂商： | FUJITSU LTD |
| 元件分类： | 图形处理器 |
| 英文描述： | Graphics Display Controller |
| 中文描述： | GRAPHICS PROCESSOR, PQFP256 |
| 封装： | 0.40 MM PITCH, PLASTIC, QFP-256 |
| 文件页数： | 7/25页 |
| 文件大小： | 236K |
| 代理商： | MB86292PFFS-G-BND |
MB86292
7
Video Capture Interface Pins
Pin Name
Note : The video capture interface inputs digital video signals in the ITU-RBT-656 format.
Graphics Memory Interface Pins
Pin Name
Notes :
The graphics memory interface connects the MB86292 to the external memory used for graphical image
data. The interface can directly accept 128-Mbit SDRAM or 64-Mbit SDRAM (with a 16-bit or 32-bit
data bus) without any external circuit.
Memory bus data can be selected between 64 bits and 32 bits. To use 32-bit data, leave the MD32-MD63
and MDQM4-7 pins open in the eight-bit RGB output mode (RGBEN pin
=
0) or the MD32-MD54 and
MDQM4-7 pins open in the eight-bit RGB output mode (RGBEN pin
=
0).
Connect the MCLKI pin to the MCLKO pin.
When RGBEN is fixed to 1, MD55-MD63 can be used as graphics memory bus data. When RGBEN is
fixed to 0, RGB0-2 is output.
Clock Input Pins
Pin Name
Input/output
*1 : Do not connect anything.
*2 : Input the "H" level.
Notes :
The clock input block inputs the clock signal that serves as the basis for the reference clock for the internal
operating clock and display dot clock. Usually input 4 Fsc (
=
14.31818 MHz for NTSC). The internal PLL
generates the internal operating clock signal of 100 MHz and the display reference clock signal of 200 MHz.
The internal operating clock signal to be used can be selected between the clock signal (100 MHz)
generated by the internal PLL and the bus clock BCLKI input to the host CPU interface. Select the BCLKI
input to use the host CPU bus at 100 MHz.
Input/output
Function
CCLK
Input
Digital video input clock signal input
VI0-VI7
Input
Digital video data input
Input/output
Function
MD0-MD54
Input/output
Graphics memory bus data
MD55-MD63
Input/output
Graphics memory bus data or RGB0-RGB2 output
MA0-MA13
Output
Graphics memory bus data
MRAS
Output
Row address strobe
MCAS
Output
Column address strobe
MWE
Output
Write enable
MDQM0-MDQM7
Output
Data mask
MCLKO
Output
Graphics memory clock output
MCLKI
Input
Graphics memory clock input
Function
CLK
Input
Clock input signal
S
Input
PLL reset signal
CKM
Input
Clock mode signal
CLKSEL [1 : 0]
Input
Clock rate select signal
OSCOUT*
1
Input/output
For connection of crystal oscillator (Reserved)
OSCCNT*
2
Input
Crystal oscillator select pin (Reserved)
相关PDF资料 |
PDF描述 |
|---|---|
| MB86293 | Grraphiics Conttrrollllerr Speciiffiicattiions |
| MB86294 | Grraphiics Controller specifications |
| MB86294S | Grraphiics Controller specifications |
| MB86295S | PCI Graphics Controller Specification |
| MB86295 | PCI Graphics Controller Specification |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86293 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Grraphiics Conttrrollllerr Speciiffiicattiions |
| MB86294 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Grraphiics Controller specifications |
| MB86294S | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:Grraphiics Controller specifications |
| MB86294SPB-GS-JXE1 | 制造商:FUJITSU 功能描述: |
| MB86295 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:PCI Graphics Controller Specification |
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