C O N T E N T S
1
GENERAL............................................................................................................................11
1.1
P
REFACE
.....................................................................................................................11
1.2
F
EATURES
....................................................................................................................12
1.3
B
LOCK
D
IAGRAM
...........................................................................................................13
1.4
F
UNCTIONAL
O
VERVIEW
.................................................................................................14
1.4.1
Host CPU interface.................................................................................................14
1.4.2
E xternal memory interface .....................................................................................16
1.4.3
Display controller ...................................................................................................17
1.4.4
Video Capture.........................................................................................................19
1.4.5
Geometry processing...............................................................................................19
1.4.6
2D Drawing ............................................................................................................20
1.4.7
3D Drawing ............................................................................................................22
1.4.8
Special effects.........................................................................................................23
1.4.9
Others ....................................................................................................................26
2
PINS ....................................................................................................................................27
2.1
S
IGNALS
......................................................................................................................27
2.1.1
Signal lines.............................................................................................................27
2.2
P
IN
A
SSIGNMENT
..........................................................................................................28
2.2.1
PBGA256 Pin assignment diagram (TOP_VIE W)....................................................28
2.2.2
PBGA256 Pin assignment table ..............................................................................29
2.2.3
HQFP256 Pin assignment diagram.........................................................................30
2.2.4
HQFP256 Pin assignment table..............................................................................31
2.3
P
IN
F
UNCTION
..............................................................................................................33
2.3.1
Host CPU interface.................................................................................................33
2.3.2
Video output interface.............................................................................................35
2.3.3
Video Capture interface..........................................................................................36
2.3.4
Graphics memory interface.....................................................................................37
2.3.5
Clock input .............................................................................................................38
2.3.6
Test pins.................................................................................................................39
2.3.7
Reset sequence.......................................................................................................39
3
PROCEDURE OF THE HARDWARE INITIALIZATION ...........................................................40
3.1
H
ARDWARE RESET
.........................................................................................................40
3.2
R
E
-
RESET
....................................................................................................................40
3.3
S
OFTWARE RESET
.........................................................................................................40
4
HOST INTERFACE...............................................................................................................41