12.1.1
CPU read/write timing diagram in SH3 mode (Normally Not Ready Mode)...........256
12.1.2
CPU read/write timing diagram in SH3 mode (Normally Ready Mode) .................257
12.1.3
CPU read/write timing diagram in SH4 mode (Normally Not Ready Mode)...........258
12.1.4
CPU read/write timing diagram in SH4 mode (Normally Ready Mode) .................259
12.1.5
CPU read/write timing diagram in V832 mode (Normally Not Ready Mode) .........260
12.1.6
CPU read/write timing diagram in V832 mode (Normally Ready Mode) ................261
12.1.7
CPU read/write timing diagram in SPARClite (Normally Not Ready Mode)..........262
12.1.8
CPU read/write timing diagram in SPARClite (Normally Ready Mode).................263
12.1.9
SH4 single-address DMA write (transfer of 1 long word).......................................264
12.1.10
SH4 single-address DMA write (transfer of 8 long words)..................................265
12.1.11
SH3/4 dual-address DMA (transfer of 1 long word)............................................266
12.1.12
SH3/4 dual-address DMA (transfer of 8 long words)...........................................266
12.1.13
V832 DMA transfer ...........................................................................................267
12.1.14
SH4 single-address DMA transfer end timing....................................................268
12.1.15
SH3/4 dual-address DMA transfer end timing ...................................................268
12.1.16
V832 DMA transfer end timing..........................................................................269
12.1.17
SH4 dual DMA write without ACK ....................................................................270
12.1.18
Dual-address DMA (without ACK ) end timing...................................................271
12.2
G
RAPHICS
M
EMORY
I
NTERFACE
.....................................................................................272
12.2.1
Timing of read access to same row address ...........................................................272
12.2.2
Timing of read access to different row addresses...................................................273
12.2.3
Timing of write access to same row address ..........................................................274
12.2.4
Timing of write access to different row addresses..................................................275
12.2.5
Timing of read/write access to same row address ..................................................276
12.2.6
Delay between ACTV commands...........................................................................277
12.2.7
Delay between Refresh command and next ACTV command.................................277
12.3
D
ISPLAY
T
IMING
..........................................................................................................278
12.3.1
Non-interlace mode...............................................................................................278
12.3.2
Interlace video mode.............................................................................................279
12.3.3
Composite synchronous signal ..............................................................................280
12.4
CPU C
AUTIONS
..........................................................................................................280
12.5
SH3 M
ODE
................................................................................................................281
12.6
SH4 M
ODE
................................................................................................................281
12.7
V832 M
ODE
...............................................................................................................282
12.8
SPARC
LITE
...............................................................................................................282
12.9
S
UPPORTED
DMA T
RANSFER
M
ODES
............................................................................282
13
ELECTRICAL CHARACTERISTICS ....................................................................................283
13.1
I
NTRODUCTION
...........................................................................................................283
13.2
M
AXIMUM
R
ATING
........................................................................................................283