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参数资料
| 型号： | MB86831-66PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 13/56页 |
| 文件大小： | 266K |
| 代理商： | MB86831-66PFV-G |
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SPARClite Series 32-Bit RISC Embedded Processor
20
Fujitsu Microelectronics, Inc.
The IRC Mode Register is used to enable the interrupt controller.
When the IRCMD bits in this register are 00(2), the interrupt
controller is disabled, and the encoded IRL<3:0> is passed to the
IU as received from an external interrupt controller. When the
IRCMD bits are 01(2), the interrupt controller is enabled, and the
IRL<3:0> pins become interrupt request inputs IRQ<15:12>.
Interrupt Controller Operation
The interrupt controller is enabled by setting the IRCMD bits of the
IRC Mode Register to 01(2).The interrupt requests then come from
IRQ<15:1>.The number of interrupt inputs available at pins varies
depending on how IRC resources are programmed. Interrupt
requests are stored in the Request Sense Register when their trigger
mode conditions are met. Of the stored interrupts not masked in the
Interrupt Mask Register, those with the highest priority are encoded
and stored in the IRL Latch/Clear Register.
If the IRL Mask (IM) bit in the Interrupt Mask Register is clear, the
IRL is passed to the CPU.The interrupt is acknowledged by setting
the CL bit of the IRL Latch/Clear Register, which clears the current
IRL and allows the next interrupt level to be loaded.
If unmasked interrupt requests are pending in the Request Sense
Register, they are loaded into the IRL Latch/Clear Register in order
of priority.
If the IRCMD bits of the IRC Mode Register are 00(2), the interrupt
controller is disabled and the signals on IRL<3:0> are passed to the
CPU without modication.
1.
Processing Interrupts as Traps
After reset, all of the mask bits in the Interrupt Mask Register
are set (i.e. interrupts are masked). Software should then pro-
gram the trigger modes and set bits 1 to 15 of the Request
Clear Register to clear any pending interrupts. Next, the
interrupt masks for the desired interrupts should be cleared
and the IRL mask (bit 0 in the Interrupt Mask Register)
should be cleared.
In the trap processing routine, software acknowledges the
interrupt by rst clearing the bit in the Request Clear Regis-
ter corresponding to the interrupt, then clears the IRL latch
by setting the CL bit in the IRL Latch/Clear Register. This
allows the next pending interrupt request to be stored in the
IRL latch.
2.
Processing Interrupts By Polling
a.
Polling the Request Sense Register Software can read the
masked interrupt request sense bits in the Request Sense
Register and call the corresponding service
routines when set bits are found. The service routine
acknowledges the interrupt by clearing the bit through
the Request Clear Register. This method is compatible
with the method described above, with unmasked
interrupts processed as traps and masked interrupts pro-
cessed by polling.
b.
Polling the IRL Latch/Clear Register
This is similar to processing interrupts as traps, except
software polls the IRL Latch/Clear Register without
generating traps. Unmasked interrupts are prioritized,
encoded, and loaded into the IRL latch, however the IM
bit in the Interrupt Mask Register is set, which
prevents a trap from being called. Software can poll the
IRL latch bits, call a service routine if it has any value
other than 0000(2), then use the Request Clear Register
to clear the corresponding bits in the Request Sense Reg-
ister. The service routine acknowledges the interrupt by
rst clearing the bit in the Request Clear
Register corresponding to the interrupt, then clears the
IRL latch by setting the CL bit in the IRL Latch/Clear
Register. This allows the next pending interrupt request
to be stored in the IRL latch. Because the IM bit is set,
this method is not compatible with processing some
interrupts as traps.
Clock Generator
The on-chip clock generator requires an external clock source (i.e.
there is no on-chip oscillator).The external clock frequency is the
same as the bus interface unit (BIU) operating frequency.The skew
between the internal clock and an external input clock source is
minimized through the use of an on-chip phase-locked loop.
The CPU and core logic can run at up to 5 times the frequency of
external clock (Max. BIU frequency = 33MHz.This is enabled by
the use of CLKSEL pins, as shown below.
Table 8. Clock Multiplication Factor
CLKSEL2
CLKSEL1
CLKSEL0
Internal Clock
HL
L
x1
HLH
x2
HH
L
x3
HHH
x4
LH
H
x5
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| MB86832-66PFV-G | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86831-80PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86831PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832-100PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86832-66PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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