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参数资料
| 型号： | MB86832-80PFV-G |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 80 MHz, RISC PROCESSOR, PQFP176 |
| 封装： | 24 X 24 MM, 0.50 MM PITCH, EIAJ, PLASTIC, SQFP-176 |
| 文件页数： | 5/54页 |
| 文件大小： | 269K |
| 代理商： | MB86832-80PFV-G |
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MB86832
Fujitsu Microelectronics, Inc.
13
Overview
The Fujitsu MB86832 is a high performance, 32-bit RISC processor
with up to 66, 80, or 100 MIPS peak performance at 66, 80, or 100
MHz clock frequency, respectively. Like its predecessors, the
MB86832 is based on the SPARC architecture and is upward code
compatible with previous implementations.The MB86832 has been
developed specically for the needs of embedded applications that
require high performance and high integration.
The MB86832 instruction set was designed for fast execution, with
most instructions executing in a single cycle.The Integer Unit (IU)
features a 5-stage pipeline which has been designed to handle data
interlocks, an optimized branch handler for efcient control
transfers, and a bus interface to handle single-cycle bus accesses to
on-chip memory.
An internal register le consisting of 136 registers organized into
eight overlapping windows provide rapid interrupt response time
and context switches.The register le minimizes accesses to memory
during procedure linkages and facilitates passing of parameters and
assignment of variables.
On-chip 8-Kbyte, 2-way set-associative instruction and 8-Kbyte, 2-
way set-associative data caches have been added to decouple the
processor from external memory.These caches have been designed for
maximum exibility. For example, they allow cache lines to be
locked for faster access to critical data.
Separate 32-bit on-chip instruction and data paths (i.e. Harvard-
style architecture) provide a high-bandwidth interface between the
IU and on-chip caches.These buses support single-cycle instruction
execution as well as single cycle data transfers with the cache.
The MB86832 also includes hardware for integer multiply and
divide step.The hardware support signicantly improves the
performance of these operations, with 32-bit integer multiplies
executing in 5 clock cycles, 16-bit integer multiplies in 3 cycles, and
8-bit integer multiplies in 2 cycles.
Key Features
Fast Integer Unit Instruction Execution: Simple operations make
up the bulk of instructions in most programs, so execution speed can
be greatly improved by designing these instructions to execute in as
short a time as possible. In the SPARC architecture, the majority of
instructions execute in one cycle with only a few of the more
complex, such as integer multiply, taking additional cycles.
Large Register Set: The large register set for the IU reduces the
number of required accesses to data memory.The registers are
organized in overlapping groups called register windows, which
allow registers to be reserved for high priority tasks, such as
interrupts, or for frequently called tasks such as operating system
working registers.The overlapping windows also simplify parameter
passing and reduce instruction overhead for procedure linkage.
On-Chip Caches: Separate 2-way set associative instruction and
data caches have been added to IU.This decouples the fast IU from
off-chip memory because external memory access is only required on
cache misses.
Cache Locking: Both the instruction and data cache lines can be
locked to ensure deterministic response and highest performance for
critical or frequently called routines. Maximum exibility has been
designed into the cache to allow all or selected portions to be locked.
Bus Interface: The requirement for glue logic between the
MB86832 and the system is minimized by providing programmable
chip selects, programmable wait state circuitry, programmable
cacheable and non-cacheable memory address, and support for
connection to fast page-mode DRAM or burst-mode EDO DRAM.
Multiple bus masters are supported through a simple handshaking
protocol.The MB86832 can boot from either 8-, 16-, or 32-bit wide
memory. In addition, the programmable data bus allows reading/
writing of different memory widths.
For high frequency operation, the core can run at up to 5 times the
bus. Note however, that the BIU frequency should not exceed 40
MHz for the 100 MHz version and 33 MHz for the 66 and 80 MHz
version.
Clock Generator:An external clock source must be supplied. Unlike
some other members of the SPARClite family, there is no on-chip
oscillator.A built-in phase-locked loop minimizes the skew between
on and off-chip clocks.
Enhanced Instruction Set: The MB86832 includes a fast integer
multiply instruction which executes in 5, 3, or 2 cycles for 32-bit,
16-bit, or 8-bit multiplicands, respectively.An integer divide-step
instruction cuts divide times by a factor of 10 over previous SPARC
implementations.A scan instruction supports a single cycle search
for the most signicant 1 or 0 in a word or bit differing from sign
bit.
相关PDF资料 |
PDF描述 |
|---|---|
| MB86832-66PFV-G | 32-BIT, 66 MHz, RISC PROCESSOR, PQFP176 |
| MB86860 | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| MB86931-20ZF-G | 32-BIT, 20 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86931-40ZF-G | 32-BIT, 40 MHz, RISC MICROCONTROLLER, CQFP256 |
| MB86933H-20PF-G | 32-BIT, 20 MHz, RISC PROCESSOR, PQFP160 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MB86833 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86833PMT2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834-120PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
| MB86834PFV | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Embedded Controller |
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