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参数资料
| 型号： | MB881631BPN-G-ERE1 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 26 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封装： | 2 X 2 MM, 0.75 MM HEIGHT, 0.50 MM PITCH, PLASTIC, SON-8 |
| 文件页数： | 3/19页 |
| 文件大小： | 685K |
| 代理商： | MB881631BPN-G-ERE1 |
MB88163
DS04-29137-3E
11
Lock-Up time
If the setting pin is fixed at “H” level or “L” level, the maximum time after the power is turned on until the set
clock is output from OUT is (the stabilization wait time of input clock to XIN pin)
+ (the Lock-Up time “tLK”).
For the input clock stabilization wait time, check the characteristics of the resonator or oscillator used.
If the S0 pin and the S1 pin are used for modulation control during normal operation, the set clock is output
from the OUT pin within the Lock-Up time “tLK” after the level at the pin is determined.
Note: The wait time for the clock signal output from the OUT pin to become stable is required after the IC is
released from the S0 pin and the S1 pin are changed. During the period until the output clock signal
becomes stable, the output frequency, output clock duty cycle, modulation period, and Cycle-Cycle jitter
characteristic cannot be guaranteed. It is therefore advisable to perform processing such as cancelling
a reset of the device at the succeeding stage after the Lock-Up time.
VDD
S0, S1
XIN
OUT
1.65 V
VIH
Input clock
oscillation stabilization wait time
tLK (Lock-Up time)
VDD
XIN
VIH
VIL
S0, S1
tLK (Lock-Up time)
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| MB881631BPN-G-EFE1 | 26 MHz, OTHER CLOCK GENERATOR, PDSO8 |
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