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参数资料
| 型号： | MB881822APVA1-G-EFE1 |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PBCC20 |
| 封装： | 3.50 X 3.50 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, PLASTIC, BCC-20 |
| 文件页数： | 7/32页 |
| 文件大小： | 919K |
| 代理商： | MB881822APVA1-G-EFE1 |
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MB88182
DS04-29138-1E
15
<Command>
Set for the CLK2, CLK3 and CLK4 setting registers with either individual or successive settings. Settings other
than those in the following table are prohibited.
<Register setting for writing data>
Transfer data from the upper address. When writing successively to the setting registers of multiple clocks, the
data will be written from the setting registers CLK1, CLK2, CLK3 and to CLK4 in order.
<Bus format for reading register>
: Transmit from master device
: Transmit from this device (slave)
S : START condition
A : Acknowledge
P : STOP condition
When reading data, the data will be output from the upper address of the CLK1 setting register, then CLK2
setting register, CLK3 setting register, CLK4 setting register, in order. The data will be output 22 bytes in total.
Note: When all outputs in this device are powered down, the I2C function also stops. Therefore, setting by the I2C
should be performed when the CKREF clock is being output.
Command
(8-bit)
C7
C6
C5
C4
C3
C2
C1
C0
Transfer
bytes
00000001
4
Set to CLK1 setting register
00000010
6
Set to CLK2 setting register
00000100
6
Set to CLK3 setting register
00001000
6
Set to CLK4 setting register
00001111
22
Successive set to all registers
0000
Other than “0000” or
those above
10 to 18
Successive set to the register
corresponding to the bit which is set “1”.
first S6
S0 R/W
D7
D0
D7
D0
Last
S
Slave address
(7 bit)
1A
CLK1 setting register
bit31-24 output
A
CLK1 setting register
bit23-16 output
A
output register
values
A
P
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