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参数资料
| 型号： | MB881822BWQN-G-JN-ERE1 |
| 厂商： | FUJITSU LTD |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 100 MHz, OTHER CLOCK GENERATOR, PQCC24 |
| 封装： | 2.50 X 3.50 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, PLASTIC, QFN-24 |
| 文件页数： | 1/32页 |
| 文件大小： | 938K |
| 代理商： | MB881822BWQN-G-JN-ERE1 |
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FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright2009-2010 FUJITSU SEMICONDUCTOR LIMITED All rights reserved
2010.9
ASSP
Spread Spectrum Clock Generator
MB88182
■ DESCRIPTION
MB88182 is the multi-output clock generator for EMI (Electro Magnetic Interference) reduction. The peak of
unnecessary radiation noise (EMI) can be attenuated by making the oscillation frequency slightly modulate
periodically with the internal modulator.
It is possible to set the frequency in the built-in register using the I2C bus that can vary depending on the application.
■ FEATURES
Built-in PLL : 3
Without spread-spectrum function : 1 (PLL)
With spread-spectrum function : 2 (SSCG1, SSCG2)
Clock output pins : 5 pins
CLK1 : Clock output when setting to CLK1 (PLL).
CLK2 : Clock output when setting to CLK2 (SSCG1) .
CLK3 : Clock output when setting to CLK3 (SSCG2) .
CLK4 : Clock output when setting to CLK4 (SSCG2) .
Note: It is not possible to output CLK3 and CLK4 at the same time except when outputting the same frequency to
CLK3 and CLK4.
CKREF : Buffered output for CKIN clock.
Power down pins : 5 pins
XPD1 : Control the stop state of PLL and the CLK1 output.
XPD2 : Control the stop state of SSCG1 and the CLK2 output.
XPD3 : Control the stop state of the CLK3 output.
XPD4 : Control the stop state of the CLK4 output.
Note: Halting both CLK3 and CLK4 stops operating the SSCG2.
XPDREF: Control the stop state of the CKREF output.
(Continued)
DS04-29138-5E
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