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参数资料
| 型号： | MB89PV960CF |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROCONTROLLER, CQFP48 |
| 封装： | 0.80 MM PITCH, CERAMIC, MQFP-48 |
| 文件页数： | 15/48页 |
| 文件大小： | 578K |
| 代理商： | MB89PV960CF |
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MB89960 Series
22
The RP contains the address of the currently used register bank. The conversion diagram below shows the
relationship between the RP value and actual address.
CCR contains bits that indicate the result of an arithmetic operation or information about transfer data and bits
used to control CPU operation when an interrupt occurs.
H-flag
: Set to “1” when a carry from bit 3 to bit 4 or a borrow from bit 4 to bit 3 occurs as a result of an
arithmetic operation. Cleared to “0” otherwise. This flag is for decimal adjustment instructions and
should be ignored for operations other than addition and subtraction.
I-flag
: Interrupts are enabled when this flag is set to “1” and disabled when the flag is set to “0”. Cleared
to “0” by a reset.
IL1, 0
: Indicates the level of interrupts currently allowed. The CPU only processes interrupts with a re-
quest level higher than the value indicated by these bits.
IL1
IL0
Interrupt Level
Priority
00
1
High
Low
= No interrupt
01
10
2
11
3
N-flag
: Set to “1” when the MSB of the result of an arithmetic operation is “1” and cleared to “0” when the
MSB is “0”.
Z-flag
: Set to “1” when the result of an arithmetic operation is zero. Cleared to “0” otherwise
V-flag
: Set to “1” when a 2’s complement overflow occurs as the result of an arithmetic operation. Cleared
to “0” if no 2’s complement overflow occurs.
C-flag
: Set to “1” when a carry from bit 7 or a borrow to bit 7 occurs as the result of an arithmetic opera-
tion. Cleared to “0” otherwise. Set to the shift-out value in the case of a shift instruction.
"0"
"1"
R4
R3
R2
R1
R0
b2
b1
b0
A7
A6
A5
A4
A3
A2
A1
Upper (RP)
Lower (op code)
A0
A15
Actual address
A14 A13 A12 A11 A10
A9
A8
Rules for converting of actual addresses of the general-purpose register area
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