MB90246APFV PDF资料下载(91/100 页)16-bit Proprietary Microcontroller

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参数资料

型号：	MB90246APFV
厂商：	FUJITSU LTD
元件分类：	微控制器/微处理器
英文描述：	16-bit Proprietary Microcontroller
中文描述：	16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP100
封装：	PLASTIC, LQFP-100
文件页数：	91/100页
文件大小：	1956K
代理商：	MB90246APFV

91

MB90246A Series

Table 19 Shift Type Instruction (Byte, Word, Long) [27 Instructions]

Note: For (a) and (b), refer to “Table 4 Number of Execution Cycles in Addressing Modes” and “Table 5 Correction

Values for Number of Cycles for Calculating Actual Number of Cycles.”

*1: Set to 3 when R0 is 0, otherwise 3 + (R0).

*2: Set to 3 when R0 is 0, otherwise 4 + (R0).

*3: Set to 3 when imm8 is 0, otherwise 3 + imm8.

*4: Set to 3 when imm8 is 0, otherwise 4 + imm8.

Mnemonic

#

~

B

Operation

LH AH

I

S

T

N

Z

V

C

RMW

RORC A

ROLC A

RORC ear

RORC eam

ROLC ear

ROLC eam

ASR

LSR

LSL

A, R0

A, R0

A, R0

ASR

LSR

LSL

A, #imm8

A, #imm8

A, #imm8

2

2

2

2 +

2

2 +

2

2

2

3

3

3

2

2

2

3 + (a)

2

3 + (a)

*1

*1

*1

*3

*3

*3

0

0

0

2

×

(b)

0

2

×

(b)

0

0

0

0

0

0

byte (A)

←

With right-rotate carry

byte (A)

←

With left-rotate carry

byte (ear)

←

With right-rotate carry

byte (eam)

←

With right-rotate carry

byte (ear)

←

With left-rotate carry

byte (eam)

←

With left-rotate carry

byte (A)

←

Arithmetic right barrel shift (A, R0)

byte (A)

←

Logical right barrel shift (A, R0)

byte (A)

←

Logical left barrel shift (A, R0)

byte (A)

←

Arithmetic right barrel shift (A, imm8)

byte (A)

←

Logical right barrel shift (A, imm8)

byte (A)

←

Logical left barrel shift (A, imm8)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

–

*

*

–

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

–

–

–

–

–

–

–

–

–

–

–

–

*

*

*

*

*

*

*

*

*

*

*

*

–

–

*

*

*

*

–

–

–

–

–

–

ASRW A

LSRW

A/SHRW

A

LSLW

A/SHLW A

ASRW A, R0

LSRW A, R0

LSLW A, R0

ASRW

A, #imm8

LSRW

A, #imm8

LSLW

A, #imm8

1

1

1

2

2

2

3

3

3

2

2

2

*1

*1

*1

*3

*3

*3

0

0

0

0

0

0

0

0

0

word (A)

←

Arithmetic right shift (A, 1 bit)

word (A)

←

Logical right shift (A, 1 bit)

word (A)

←

Logical left shift (A, 1 bit)

word (A)

←

Arithmetic right barrel shift (A, R0)

word (A)

←

Logical right barrel shift (A, R0)

word (A)

←

Logical left barrel shift (A, R0)

word (A)

←

Arithmetic right barrel shift (A, imm8)

word (A)

←

Logical right barrel shift (A, imm8)

word (A)

←

Logical left barrel shift (A, imm8)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

–

*

*

–

*

*

–

*

R

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

*

–

–

–

–

–

–

–

–

–

*

*

*

*

*

*

*

*

*

–

–

–

–

–

–

–

–

–

ASRL A, R0

LSRL A, R0

LSLL

A, R0

ASRL

LSRL

LSLL

A, #imm8

A, #imm8

A, #imm8

2

2

2

3

3

3

*2

*2

*2

*4

*4

*4

0

0

0

0

0

0

long (A)

←

Arithmetic right barrel shift (A, R0)

long (A)

←

Logical right barrel shift (A, R0)

long (A)

←

Logical left barrel shift (A, R0)

long (A)

←

Arithmetic right barrel shift (A, imm8)

long (A)

←

Logical right barrel shift (A, imm8)

long (A)

←

Logical left barrel shift (A, imm8)

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

–

*

*

–

*

*

–

*

*

*

*

*

*

*

*

*

*

*

*

–

–

–

–

–

–

*

*

*

*

*

*

–

–

–

–

–

–

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