参数资料
型号: MB90522BPMC1
厂商: FUJITSU LTD
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP120
封装: 14 X 14 MM, 1.70 MM HEIGHT, 0.40 MM PITCH, PLASTIC, LQFP-120
文件页数: 54/96页
文件大小: 2960K
代理商: MB90522BPMC1
MB90520B Series
66
DS07-13707-5E
15. Clock Timer
The clock timer is a 15-bit freerun timer that counts up synchronized with the sub-clock.
Seven different interval time settings are available.
This timer provides the clock for the sub-clock’s oscillation stabilization delay timer and the watchdog timer.
This timer always counts the sub-clock, regardless of the settings in the clock selection register (CKSC) .
Clock timer functions
Clock timer interval times
SCLK : Sub-clock frequency
The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.
Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock
operates at 32.768 kHz.
Clock periods generated by clock timer
SCLK : Sub-clock frequency
The values enclosed in ( ) are the times for a sub-clock frequency of 8.192 kHz.
Note that the sub-oscillation clock is divided by four to generate the sub-clock frequency. The sub-oscillation clock
operates at 32.768 kHz.
Function
Interval time
Selectable from the seven settings shown in the table below.
Clock timer size
15-bit
Clock supply
Oscillation stabilization delay timer for sub-clock and watchdog timer
Source clock
Sub-oscillation clock divided by four. (SCLK : Sub-clock)
Interrupts
Interval time overflow
EI2OS support
Not supported by the extended intelligent I/O service (EI2OS) .
Sub-Clock Period
Interval Time
SCLK (122
s)
29/SCLK (approx. 62.5 ms)
210/SCLK (approx. 125.0 ms)
211/SCLK (approx. 250.0 ms)
212/SCLK (approx. 500.0 ms)
213/SCLK (approx. 1.0 s)
214/SCLK (approx. 2.0 s)
216/SCLK (approx. 4.0 s)
Clock Supply
Clock Period
Oscillation stabilization delay timer
for sub-clock
214/SCLK (approx. 2.0 s)
Watchdog timer
210/SCLK (approx. 125.0 ms)
213/SCLK (approx. 1.0 s)
214/SCLK (approx. 2.0 s)
216/SCLK (approx. 4.0 s)
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