参数资料
型号: MB90561P
元件分类: 微控制器/微处理器
英文描述: 16-BIT, MROM, 16 MHz, MICROCONTROLLER, PDIP64
封装: 1.788 MM PITCH, SHRINK, PLASTIC, DIP-64
文件页数: 44/91页
文件大小: 931K
代理商: MB90561P
MB90560/565 Series
49
8.
Delayed Interrupt Generation Module
The delayed interrupt generation module is used to generate the task switching interrupt. Generation of this
hardware interrupt can be specified by software.
Delayed interrupt generation module functions
Block diagram
Function and Control
Interrupt trigger
Writing “1” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0
= 1) generates an interrupt request.
Writing “0” to bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0
= 1) clears the interrupt request.
Interrupt control
No enable/disable register is provided for this interrupt.
Interrupt flag
Set in bit R0 of the delayed interrupt request generation/clear register
(DIRR : R0) .
EI2OS support
Not supported by the extended intelligent I/O service (EI2OS) .
R0
Internal data bus
Delayed interrupt request generation/
clear register (DIRR)
S
R
Interrupt
request signal
Interrupt request
latch
: Undefined
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相关代理商/技术参数
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