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| 型号： | MB91F356BPMT |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | RISC MICROCONTROLLER, PQFP176 |
| 封装： | 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PPITCH, LEAD FREE, PLASTIC, LQFP-176 |
| 文件页数： | 60/140页 |
| 文件大小： | 3803K |
| 代理商： | MB91F356BPMT |
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MB91350A Series
26
DS07-16503-5E
Prefetch
If prefetch is enabled in a area that is configured as little endian, limit access to the corresponding area to
word-length (32-bit) access.
Byte or halfword does not allow a proper access to data.
I/O Port Access
Ports can only be accessed in bytes.
Built-in RAM
Immediately after a reset is released, the internal RAM capacity restriction function begins operating, allowing
only 4 Kbytes to be used for both data and program execution irrespective of the on-chip RAM capacity.
Update the setting to clear the restriction function.
At least one NOP instruction is required immediately after updating this setting.
Please refer to the “MB91350A Series HARDWARE MANUAL CHAPTER 19 DATA INTERNAL RAM/INSTRUC-
TION INTERNAL RAM ACCESS RESTRICTION FUNCTIONS” for the details.
Flash Memory
In programming mode, Flash memory cannot be used for the interrupt vector table (However, a reset can be
performed) .
Notes on the PS Register
As the PS register is processed in advance by some instructions, when the debugger is being used, the following
exception handling may result in execution breaking in an interrupt handling routine or the displayed values of
the flags in the PS register being updated.
As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event,
the operation before and after the EIT always proceeds according to specification.
1. The following behavior may occur if any of the following occurs in the instruction immediately after a DIV0U/
DIV0S instruction :
(a) a user interrupt or NMI is accepted; (b) single-step execution is performed; or (c) execution breaks due
to a data event or from the emulator menu.
The D0 and D1 flags are updated in advance.
An EIT handling routine (user interrupt, NMI, or emulator) is executed.
Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are
updated to the same values as in (1).
2. The following behavior occurs when an ORCCR, STILM, MOV Ri or PS instruction is executed to enable a
user interrupt or NMI source while that interrupt is in the active state.
The PS register is updated in advance.
The EIT handling routine (user interrupt, NMI, or emulator) is executed.
Upon returning from the EIT, the above instructions are executed and the PS register is updated to the
same value as in (1).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB91F357B | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F357BPMT | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit Microcontroller |
| MB91F361GAPFVS | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller |
| MB91F362GAPFVS | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller |
| MB91F362GAPFVS-G-N2E1 | 功能描述:IC MCU 32BIT 512KB FLASH 制造商:cypress semiconductor corp 系列:FR MB91360G 零件状态:在售 核心处理器:FR50 RISC 核心尺寸:32-位 速度:64MHz 连接性:CAN，I2C，串行输入/输出，UART/USART 外设:DMA，POR，PWM，WDT I/O 数:160 程序存储容量:512KB（512K x 8） 程序存储器类型:闪存 EEPROM 容量:- RAM 容量:20K x 8 电压 - 电源（Vcc/Vdd）:4.25 V ~ 5.25 V 数据转换器:A/D 8x10b，D/A 2x10b 振荡器类型:外部 工作温度:-40°C ~ 85°C（TA） 标准包装:24 |
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