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参数资料
| 型号： | MB95F106ANSPMC |
| 厂商： | FUJITSU LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 16.25 MHz, RISC MICROCONTROLLER, PQFP64 |
| 封装： | PLASTIC, LQFP-64 |
| 文件页数： | 52/72页 |
| 文件大小： | 1758K |
| 代理商： | MB95F106ANSPMC |
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MB95100AM Series
56
DS07-12614-6E
(Vcc
= 5.0 V ± 10%, AVss = Vss = 0.0 V, TA = 40 °C to + 85 °C)
(Continued)
Parameter
Sym-
bol
Pin
name
Condition
Value*2
Unit
Remarks
Min
Max
SCL clock “L” width
tLOW
SCL0
R
= 1.7 kΩ,
C
= 50 pF*1
(2
+ nm / 2) tMCLK 20
ns
Master mode
SCL clock “H” width
tHIGH
SCL0
(nm
/ 2) tMCLK 20
(nm
/ 2 ) tMCLK + 20
ns
Master mode
Start condition hold
time
tHD;STA
SCL0
SDA0
(
1 + nm / 2) tMCLK 20 (1 + nm) tMCLK + 20
ns
Master mode
Maximum value is
applied when m, n
= 1, 8.
Otherwise, the minimum
value is applied.
Stop condition setup
time
tSU;STO
SCL0
SDA0
(1
+ nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition setup
time
tSU;STA
SCL0
SDA0
(1
+ nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Bus free time between
stop condition and
start condition
tBUF
SCL0
SDA0
(2 nm
+ 4) tMCLK 20
ns
Data hold time
tHD;DAT
SCL0
SDA0
3 tMCLK
20
ns
Master mode
Data setup time
tSU;DAT
SCL0
SDA0
(
2 + nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20 ns
Master mode
When assuming that “L”
of SCL is not extended,
the minimum value is
applied to first bit of
continuous data.
Otherwise, the maximum
value is applied.
Setup time between
clearing interrupt and
SCL rising
tSU;INT SCL0
(nm
/ 2) tMCLK 20
(1 + nm
/ 2) tMCLK + 20
ns
Minimum value is
applied to interrupt at 9th
SCL
↓.
Maximum value is
applied to interrupt at 8th
SCL
↓.
SCL clock “L” width
tLOW
SCL0
4 tMCLK
20
ns
At reception
SCL clock “H” width
tHIGH
SCL0
4 tMCLK
20
ns
At reception
Start condition
detection
tHD;STA
SCL0
SDA0
2 tMCLK
20
ns
Undetected when 1 tMCLK
is used at reception
Stop condition
detection
tSU;STO
SCL0
SDA0
2 tMCLK
20
ns
Undetected when 1 tMCLK
is used at reception
Restart detection
condition
tSU;STA
SCL0
SDA0
2 tMCLK
20
ns
Undetected when 1 tMCLK
is used at reception
Bus free time
tBUF
SCL0
SDA0
2 tMCLK
20
ns
At reception
Data hold time
tHD;DAT
SCL0
SDA0
2 tMCLK
20
ns
At slave transmission
mode
Data setup time
tSU;DAT
SCL0
SDA0
tLOW
3 tMCLK 20
ns
At slave transmission
mode
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