参数资料
型号: MB95F128DPF-GE1
厂商: Fujitsu Semiconductor America Inc
文件页数: 52/67页
文件大小: 0K
描述: IC MCU FLASH 60K ROM 100QFP
标准包装: 1
系列: F²MC MB95120
核心处理器: F²MC-8FX
芯体尺寸: 8-位
速度: 16MHz
连通性: I²C,LIN,SIO,UART/USART
外围设备: LCD,LVD,POR,PWM,WDT
输入/输出数: 87
程序存储器容量: 60KB(60K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.3 V
数据转换器: A/D 12x8/10b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-QFP
包装: 托盘
产品目录页面: 722 (CN2011-ZH PDF)
其它名称: 865-1073
MB95120 Series
56
(VCC
= 3.3 V, AVSS = VSS = 0.0 V, TA = 40 °C to + 85 °C)
(Continued)
Parameter
Sym-
bol
Pin
name
Condi-
tions
Value*2
Unit
Remarks
Min
Max
SCL clock
“L” width
tLOW
SCL0
R
= 1.7 k,
C
= 50 pF*1
(2
+ nm / 2) tMCLK 20
ns
Master mode
SCL clock
“H” width
tHIGH
SCL0
(nm
/ 2) tMCLK 20
(nm
/ 2 ) tMCLK + 20
ns
Master mode
Start condition
hold time
tHD;STA
SCL0
SDA0
(
1 + nm / 2) tMCLK 20
(
1 + nm) tMCLK + 20
ns
Master mode
Maximum value is
applied when m,
n
= 1, 8.
Otherwise, the
minimum value is
applied.
Stop condition
setup time
tSU;STO
SCL0
SDA0
(1
+ nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Start condition
setup time
tSU;STA
SCL0
SDA0
(1
+ nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20
ns
Master mode
Bus free time
between stop
condition and
start condition
tBUF
SCL0
SDA0
(2 nm
+ 4) tMCLK 20
ns
Data hold time tHD;DAT
SCL0
SDA0
3 tMCLK
20
ns
Master mode
Data setup
time
tSU;DAT
SCL0
SDA0
(
2 + nm / 2) tMCLK 20 (1 + nm / 2) tMCLK + 20 ns
Master mode
When assuming
that “L” of SCL is
not extended, the
minimum value is
applied to first bit
of continuous
data.
Otherwise,
the maximum
value is applied.
Setup time
between
clearing
interrupt and
SCL rising
tSU;INT SCL0
(nm
/ 2) tMCLK 20
(1 + nm
/ 2) tMCLK + 20
ns
Minimum value is
applied to interrupt
at 9th SCL
↓.
Maximum value is
applied to interrupt
at 8th SCL
↓.
SCL clock “L”
width
tLOW
SCL0
4 tMCLK
20
ns
At reception
SCL clock “H”
width
tHIGH
SCL0
4 tMCLK
20
ns
At reception
Start condition
detection
tHD;STA
SCL0
SDA0
2 tMCLK
20
ns
Undetected when
1 tMCLK is used at
reception
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