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参数资料
| 型号： | MB95R203APF-G-JNE2 |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 10 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 12.70 X 7.50 MM, 2.65 MM HEIGHT, 1.27 MM PITCH, PLASTIC, SOP-20 |
| 文件页数： | 20/56页 |
| 文件大小： | 2023K |
| 代理商： | MB95R203APF-G-JNE2 |
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MB95R203A
DS07-12630-2E
27
(2) Source Clock/Machine Clock
(Vcc
= 3.3 V, Vss = 0.0 V, TA = 40 °C to +85 °C)
*1 : Clock before setting division due to machine clock division ratio selection bit (SYCC : DIV1 and DIV0) .
This source clock is divided by the machine clock division ratio selection bit (SYCC : DIV1 and DIV0) ,
and it becomes the machine clock. Further, the source clock can be selected as follows.
Main clock divided by 2
Main CR clock
Sub clock divided by 2
Sub CR clock divided by 2
*2 : Operation clock of the microcontroller. Machine clock can be selected as follows.
Source clock (no division)
Source clock divided by 4
Source clock divided by 8
Source clock divided by 16
Parameter
Symbol
Pin
name
Value
Unit
Remarks
Min
Typ
Max
Source clock
cycle time*1
(Clock before
division)
tSCLK
100
2000
ns
When using main external clock
Min : FCH
= 20 MHz, divided by 2
Max : FCH
= 1 MHz, divided by 2
125
1000
ns
When using main CR oscillation clock
Min : FCRH
= 8 MHz
Max : FCRH
= 1 MHz
61
μs
When using sub oscillation clock
FCL
= 32.768 kHz, divided by 2
20
μs
When using sub oscillation clock
FCRL
= 100 kHz, divided by 2
Source clock
frequency
FSP
0.5
10
MHz When using main oscillation clock
1
8
MHz When using main CR oscillation clock
FSPL
16.384
kHz When using sub oscillation clock
50
kHz When using sub CR clock
Machine clock
cycle time*2
(Minimum
instruction
execution time)
tMCLK
100
32000
ns
When using main oscillation clock
Min : FSP
= 10 MHz, no division
Max : FSP
= 0.5 MHz, divided by 16
100
16000
ns
When using main CR clock
Min : FSP
= 10 MHz, no division
Max : FSP
= 1 MHz, divided by 16
61
976.5
μs
When using sub oscillation clock
Min : FSPL
= 16.384 kHz, no division
Max : FSPL
= 16.384 kHz, divided by 16
20
320
μs
When using sub CR clock
Min : FSPL
= 50 kHz, no division
Max : FSPL
= 50 kHz, divided by 16
Machine clock
frequency
FMP
0.031
10
MHz When using main oscillation clock
0.0625
8
MHz When using main CR clock
FMPL
1.024
16.384
kHz When using sub oscillation clock
3.125
50
kHz When using sub CR clock
相关PDF资料 |
PDF描述 |
|---|---|
| MB95R203P-G-SH-NE2 | 8-BIT, 10 MHz, MICROCONTROLLER, PDIP24 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MB95R203AP-G-SH-JNE2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95R203PF-G-JNE2 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:8-bit Proprietary Microcontrollers |
| MB95R203P-G-SH-JNE2 | 制造商:FUJITSU 功能描述:IC MCU 8BIT 8FX 8K FRAM 24SDIP |
| MB96300 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
| MB96310 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16-bit Proprietary Microcontroller |
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