参数资料
型号: MB96F347RSBPMC-GSE2
厂商: Fujitsu Semiconductor America Inc
文件页数: 64/118页
文件大小: 0K
描述: IC MCU 416KB FLASH/ROM 100LQFP
标准包装: 1
系列: F²MC MB96340
核心处理器: F²MC-16FX
芯体尺寸: 16-位
速度: 56MHz
连通性: CAN,EBI/EMI,I²C,LIN,SCI,UART/USART
外围设备: DMA,LVD,LVR,POR,PWM,WDT
输入/输出数: 82
程序存储器容量: 416KB(416K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 24x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 100-LQFP
包装: 托盘
其它名称: 865-1084
Specication
MB96340
FME/EMDC- 2007-9-12
MB96300_DS_features.fm
5
PRELIMINARY
Programmable Pulse
Generator
16-bit down counter, cycle and duty setting registers
Interrupt at trigger, counter borrow and/or duty match
PWM operation and one-shot operation
Internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and
Reload timer overflow as clock input
Can be triggered by software or reload timer
Real Time Clock
Can be clocked either from sub oscillator (devices with partnumber suffix “W”),main
oscillator or from the RC oscillator
Facility to correct oscillation deviation of Sub clock or RC oscillator clock (clock
calibration)
Read/write accessible second/minute/hour registers
Can signal interrupts every halfsecond/second/minute/hour/day
Internal clock divider and prescaler provide exact 1s clock based on a 4 MHz or a 32
kHz clock input (devices with partnumber suffix “W”) clock input
External Interrupts
Edge sensitive or level sensitive
Interrupt mask and pending bit per channel
Each available CAN channel RX has an external interrupt for wake-up
Selected USART channels SIN have an external interrupt for wake-up
Non Maskable Interrupt
Disabled after reset
Once enabled, can not be disabled other than by reset.
Level high or level low sensitive
Pin shared with external interrupt 0.
External bus interface
8-bit or 16-bit bidirectional data
Up to 24-bit addresses
6 chip select signals
Multiplexed address/data lines
Wait state request
External bus master possible
Timing programmable
Alarm comparators
Monitors an external voltage and generates an interrupt in case of a voltage lower or
higher than the defined thresholds
Threshold voltages defined externally or generated internally
Status is readable, interrupts can be masked separately
Feature
Description
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