参数资料
型号: MB9AF102NABGL
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PBGA112
封装: 10 X 10 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-112
文件页数: 46/100页
文件大小: 1055K
代理商: MB9AF102NABGL
5
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r2.1
MB9A100A Series
CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator helps a verify data transmission or storage integrity.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
·
CCITT CRC16 Generator Polynomial: 0x1021
·
IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
Clock and Reset
[Clocks]
Five clock sources (2 ext. osc, 2 CR osc, and Main PLL) that are dynamically selectable.
·
Main Clock
: 4MHz to 48MHz
·
Sub Clock
: 32.768kHz
·
High-speed CR Clock : 4MHz
·
Low-speed CR Clock : 100kHz
·
Main PLL Clock
[Resets]
Reset requests from INITX pins, Power on reset, Software reset, watchdog timers reset, low voltage
detector reset and clock supervisor reset.
Clock Super Visor (CSV)
Clocks generated by CR oscillators are used to supervise abnormality of the external clocks.
·
External OSC clock failure (clock stop) is detected, reset is asserted.
·
External OSC frequency anomaly is detected, interrupt or reset is asserted.
Low Voltage Detector (LVD)
This series include 2-stage monitoring of voltage on the VCC. When the voltage falls below the voltage has
been set, Low Voltage Detector generates an interrupt or reset.
·
LVD1: error reporting via interrupt
·
LVD2: auto-reset operation
Low Power Mode
Three power saving modes supported.
·
SLEEP
·
TIMER
·
STOP
Debug
·
Serial Wire JTAG Debug Port (SWJ-DP)
·
Embedded Trace Macrocells (ETM) provide comprehensive debug and trace facilities.
Power Supply
·
VCC = 2.7V to 5.5V: Correspond to the wide range voltage.
DS706-00022-1v0-E
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