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参数资料
型号： MB9BF217THPMC
厂商： FUJITSU LTD
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, RISC MICROCONTROLLER, PQFP176
封装： 24 X 24 MM, 1.70 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, PLASTIC, LQFP-176
文件页数： 19/128页
文件大小： 1205K
代理商： MB9BF217THPMC
115
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r1.0
MB9B210T Series
DS706-00015-0v01-E
12bit A/D Converter
·
Electrical characteristics for the A/D converter.( Preliminary value)
(Vcc = AVcc = 2.7V to 5.5V, Vss = AVss = 0V, Ta = - 40
°C to + 85°C)
Value
Parameter
Pin
name
Min
Typ
Max
Uni
t
Remarks
Resolution
-
12
bit
Linearity error
-
- 4.5
-
+ 4.5
LS
B
Differential linearity
error
-
-2.5
-
+ 2.5
LS
B
Zero transition voltage
AN0 to
AN31
- 20
-
+ 20
mV
Full transition voltage
AN0 to
AN31
- 20
-
+ 20
mV
AVRH = 2.7V to 5.5V
Conversion time
-
1.0*1
-
μsAVcc ≥ 4.5V
*2
-
AVcc ≥ 4.5V
Sampling time
Ts
*2
-
ns
AVcc < 4.5V
AVcc ≥ 4.5V
Compare clock cycle*3
Tcck
50
-
10000
ns
AVcc < 4.5V
State transition time to
operation permission
Tstt
1.0
-
μs
-
0.47
0.62
mA A/D 1unit operation
Power supply current
(analog + digital)
AVCC
-
0.01
TBD
μA
When A/D stop (1unit)
-
1.1
1.96
mA
A/D 1unit operation
AVRH=5.5V
Reference power
supply current
(between AVRH to
AVSS)
AVRH
-
0.01
1.6
μA
When A/D stop (1unit)
Analog input capacity
Cin
-
12.9
pF
2
AVcc ≥ 4.5V
Analog input resistance
Rin
-
3.8
k
AVcc < 4.5V
Interchannel disparity
-
4
LS
B
Analog port input
current
AN0 to
AN31
-
5
μA
Analog input voltage
AN0 to
AN31
AVSS
-
AVRH
V
Reference voltage
AVRH
AVSS
-
AVCC
V
*1: Conversion time is the value of sampling time(Ts) + compare time(Tc).
The condition of the minimum conversion time is when HCLK=40MHz, the value of sampling time: 0.3μs,
the value of sampling time: 700ns (AVcc
≥ 4.5V).
Ensure that it satisfies the value of sampling time(Ts) and compare clock cycle (Tcck).
For setting*4 of sampling time and compare clock cycle, refer to chapter "Chapter:12-bit A/D Converter" in
"FM3 FAMILY MB9Axxx/MB9Bxxx Series PERIPHERAL MANUAL".
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: Compare time (Tc) is the value of (Equation 2).
*4: The register setting of the A/D Converter is reflected by the timing of the APB bus clock.
Sampling clock and compare clock are set with the base clock (HCLK).
About the APB bus number which A/D Converter is connected to, see chapter " BLOCK DIAGRAM"
in this data sheet.
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