参数资料
型号: MC100E310FN
厂商: ON Semiconductor
文件页数: 5/8页
文件大小: 0K
描述: IC CLOCK BUFFER MUX 2:8 28-PLCC
产品变化通告: Product Discontinuation 20/Aug/2008
标准包装: 37
系列: 100E
类型: 扇出缓冲器(分配),多路复用器
电路数: 1
比率 - 输入:输出: 2:8
差分 - 输入:输出: 是/是
输入: ECL,PECL
输出: ECL,PECL
频率 - 最大: 900MHz
电源电压: 4.2 V ~ 5.7 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-LCC(J 形引线)
供应商设备封装: 28-PLCC(11.51x11.51)
包装: 管件
MC100E310
http://onsemi.com
5
Table 6. AC CHARACTERISTICS VCCx = 5.0 V; VEE= 0 V or VCCx = 0 V; VEE = 5.0 V (Note 7)
40°C
25°C
85°C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
fMAX
Maximum Toggle Frequency
700
900
700
900
700
900
MHz
tPLH
tPHL
Propagation Delay to Output
IN (differential) (Note 8)
IN (singleended) (Note 9)
525
500
725
750
550
750
800
575
600
775
850
ps
tskew
WithinDevice Skew (Note 10)
ParttoPart Skew (Diff)
75
250
50
200
50
200
ps
tJITTER
Random Clock Jitter (RMS)
< 1
ps
VPP
Input Voltage Swing
(Differential Configuration)
500
mV
tr/tf
Output Rise/Fall Time
(20%80%)
200
600
200
600
200
600
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. VEE can vary 0.46 V / +0.8 V.
8. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the
differential output signals. See Definitions and Testing of ECLinPS AC Parameters in Chapter 1 (page 112) of the ON Semiconductor
High Performance ECL Data Book (DL140/D).
9. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal.
10.The withindevice skew is defined as the worst case difference between any two similar delay paths within a single device.
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