参数资料
| 型号： | MC100EL15DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 1/8页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:4 16-SOIC |
| 标准包装： | 2,500 |
| 系列： | 100EL |
| 类型： | 扇出缓冲器（分配），多路复用器 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:4 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | ECL，PECL |
| 输出： | ECL，PECL |
| 频率 - 最大： | 1.25GHz |
| 电源电压： | 4.2 V ~ 5.7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SOIC |
| 包装： | 带卷 (TR) |
Semiconductor Components Industries, LLC, 2005
August, 2005 Rev. 5
Publication Order Number:
MC10EL15/D
1
MC10EL15, MC100EL15
5VECL 1:4 Clock
Distribution Chip
The MC10EL/100EL15 is a low skew 1:4 clock distribution chip
designed explicitly for low skew clock distribution applications. The
VBB pin, an internally generated voltage supply, is available to this device
only. For single-ended input conditions, the unused differential input is
connected to VBB as a switching reference voltage. VBB may also rebias
AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF
capacitor and limit current sourcing or sinking to 0.5 mA. When not used,
VBB should be left open.
The EL15 features a multiplexed clock input to allow for the
distribution of a lower speed scan or test clock along with the high
speed system clock. When LOW (or left open and pulled LOW by the
input pulldown resistor) the SEL pin will select the differential clock
input.
The common enable (EN) is synchronous so that the outputs will
only be enabled/disabled when they are already in the LOW state. This
avoids any chance of generating a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The
internal flip flop is clocked on the falling edge of the input clock,
therefore all associated specification limits are referenced to the
negative edge of the clock input.
The 100 series contains temperature compensation.
Features
50 ps Output-to-Output Skew
Synchronous Enable/Disable
Multiplexed Clock Input
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input Pulldown Resistors on CLKs, SCLK, SEL, and EN.
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
SO16
D SUFFIX
CASE 751B
1
16
MARKING DIAGRAMS*
10EL15G
AWLYWW
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G= PbFree Package
100EL15G
AWLYWW
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
ORDERING INFORMATION
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