参数资料
型号: MC100EL51D
厂商: ON Semiconductor
文件页数: 2/9页
文件大小: 0K
描述: IC FLIP FLOP ECL DIFF CLK 8SOIC
标准包装: 98
系列: 100EL
功能: 复位
类型: D 型
输出类型: 差分
元件数: 1
每个元件的位元数: 1
频率 - 时钟: 2.8GHz
延迟时间 - 传输: 475ps
触发器类型: 正边沿
电源电压: 4.2 V ~ 5.7 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
其它名称: MC100EL51DOS
MC10EL51, MC100EL51
http://onsemi.com
2
1
2
3
45
6
7
8
Q
VEE
VCC
Figure 1. Logic Diagram and Pinout Assignment
D
Q
CLK
R
D
R
Table 1. TRUTH TABLE
D*
L
H
X
R*
L
H
CLK*
Z
X
Q**
L
H
L
Z = LOW to HIGH Transition
R
ECL Reset Input
D
ECL Data Input
CLK, CLK
ECL Clock Inputs
Q, Q
ECL Data Outputs
VCC
Positive Supply
VEE
Negative Supply
Table 2. PIN DESCRIPTION
* Pin will default low when left open.
**Pin will default low when inputs are left open.
PIN
FUNCTION
EP
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect
to the most negative supply (GND)
or leave unconnected, floating open.
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8
V
VEE
NECL Mode Power Supply
VCC = 0 V
8
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI VCC
VI VEE
6
V
Iout
Output Current
Continuous
Surge
50
100
mA
TA
Operating Temperature Range
40 to +85
°C
Tstg
Storage Temperature Range
65 to +150
°C
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
8 SOIC
190
130
°C/W
qJC
Thermal Resistance (JunctiontoCase)
Standard Board
8 SOIC
41 to 44
°C/W
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
8 TSSOP
185
140
°C/W
qJC
Thermal Resistance (JunctiontoCase)
Standard Board
8 TSSOP
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
DFN8
129
84
°C/W
Tsol
Wave Solder
Pb
PbFree
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
°C
qJC
Thermal Resistance (JunctiontoCase)
(Note 1)
DFN8
35 to 40
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
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