参数资料
| 型号： | MC100EP016FA |
| 厂商： | ON Semiconductor |
| 文件页数： | 2/13页 |
| 文件大小： | 0K |
| 描述： | IC COUNTER 8BIT SYNC ECL 32LQFP |
| 产品变化通告： | Product Obsolescence 20/Sept/2004 |
| 标准包装： | 250 |
| 系列： | 100EP |
| 逻辑类型： | 二进制计数器 |
| 方向： | 上 |
| 元件数： | 1 |
| 每个元件的位元数： | 8 |
| 复位： | 异步 |
| 计时： | 同步 |
| 计数速率： | 1.4GHz |
| 触发器类型： | 正，负 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 管件 |
| 其它名称： | MC100EP016FAOS |
MC100EP016A
http://onsemi.com
10
APPLICATIONS INFORMATION (continued)
EP01
Q0 to Q7
P0 to P7
CLK
TC
PE
CE
Figure 7. 32‐Bit Cascaded EP016A Programmable Divider
LO
CLK
MSB
LSB
EP016
EP01
Q0 to Q7
P0 to P7
EP016
CLK
TC
PE
CE
CLK
TC
PE
CE
CLK
TC
PE
CE
CLK
Figure 7 shows a typical block diagram of a 32‐bit divider
chain. Once again to maximize the frequency of operation
EP01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EP01. Note that for a
16‐bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant EP016A must also feed the
CE input of the most significant EP016A. If the two TC
outputs were OR tied the cascaded count operation would
not operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Maximizing EP016A Count Frequency
The EP016A device produces 9 fast transitioning single
ended outputs, thus VCC noise can become significant in
situations where all of the outputs switch simultaneously in
the same direction. This VCC noise can negatively impact
the maximum frequency of operation of the device. Since
the device does not need to have the Q outputs terminated to
count properly, it is recommended that if the outputs are not
going to be used in the rest of the system they should be left
unterminated. In addition, if only a subset of the Q outputs
are used in the system only those outputs should be
terminated. Not terminating the unused outputs will not only
cut down the VCC noise generated but will also save in total
system power dissipation. Following these guidelines will
allow designers to either be more aggressive in their designs
or provide them with an extra margin to the published data
book specifications.
Figure 8. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D - Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
50
W
50
W
VTT
VTT = VCC - 2.0 V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC100EP016FAG | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter |
| MC100EP016FAR2 | 功能描述:IC COUNTER 8BIT SYNC ECL 32LQFP RoHS:否 类别:集成电路 (IC) >> 逻辑 -计数器，除法器 系列:100EP 产品变化通告:1Q2012 Discontinuation 30/Mar/2012 标准包装:2,500 系列:74HC 逻辑类型:二进制计数器 方向:上 元件数:1 每个元件的位元数:12 复位:异步 计时:- 计数速率:50MHz 触发器类型:负边沿 电源电压:2 V ~ 6 V 工作温度:-55°C ~ 125°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| MC100EP016FAR2G | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:3.3V / 5V ECL 8−Bit Synchronous Binary Up Counter |
| MC100EP01D | 功能描述:逻辑门 3.3V/5V ECL 4-Input RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
| MC100EP01DG | 功能描述:逻辑门 3.3V/5V ECL 4-Input OR/NOR RoHS:否 制造商:Texas Instruments 产品:OR 逻辑系列:LVC 栅极数量:2 线路数量（输入/输出）:2 / 1 高电平输出电流:- 16 mA 低电平输出电流:16 mA 传播延迟时间:3.8 ns 电源电压-最大:5.5 V 电源电压-最小:1.65 V 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:DCU-8 封装:Reel |
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