参数资料
型号: MC100EP01DR2G
厂商: ON Semiconductor
文件页数: 7/10页
文件大小: 0K
描述: IC GATE OR/NOR ECL 4INPUT 8-SOIC
标准包装: 2,500
系列: 100EP
逻辑类型: 或非门/或门
电路数: 1
输入数: 4
施密特触发器输入:
输出类型: 差分
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
MC10EP01, MC100EP01
http://onsemi.com
6
Table 11. AC CHARACTERISTICS VCC = 3.0 V to 5.5 V; VEE = 0 V or VCC = 0 V; VEE = 3.0 V to 5.5 V (Note 15)
Symbol
Characteristic
40°C
25°C
85°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 2. Fmax/JITTER)
> 3
GHz
tPLH,
tPHL
Propagation Delay
D to Q, Q
150
260
330
150
270
330
200
300
350
ps
tJITTER
CycletoCycle Jitter
(See Figure 2. Fmax/JITTER)
0.2
< 1
0.2
< 1
0.2
< 1
ps
tr
tf
Output Rise/Fall Times
Q, Q
(20% 80%)
50
120
170
60
130
180
70
150
200
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
15.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC 2.0 V.
0
100
200
300
400
500
600
700
800
900
0
1000
2000
3000
4000
5000
6000
Figure 2. Fmax/Jitter
FREQUENCY (MHz)
V
OUTpp
(mV)
1
2
3
4
5
6
7
8
JITTER
OUT
(ps)
(RMS)
(JITTER)
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D Termination of ECL Logic Devices.)
Driver
Device
Receiver
Device
QD
Q
D
Zo = 50 W
50 W
VTT
VTT = VCC 2.0 V
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