参数资料
型号: MC100EP16VTDTR2G
厂商: ON Semiconductor
文件页数: 1/12页
文件大小: 0K
描述: IC RCVR/DRVR ECL DIFF VAR 8TSSOP
标准包装: 2,500
系列: 100EP
逻辑类型: 差分接收器/驱动器
电源电压: 3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-TSSOP
包装: 带卷 (TR)
其它名称: MC100EP16VTDTR2GOS
Semiconductor Components Industries, LLC, 2008
August, 2008 Rev. 4
1
Publication Order Number:
MC100EP16VT/D
MC100EP16VT
3.3V / 5VECL Differential
Receiver/Driver with
Variable Output Swing and
Internal Input Termination
Description
The MC100EP16VT is a differential receiver functionally equivalent
to the 100EP16 with input pins controlling the amplitude of the outputs
(pin 1) and providing an internal termination network (pin 4).
The VCTRL input pin controls the output amplitude of the EP16VT
and is referenced to VCC. (See Figure 4.) The operational range of the
VCTRL input is from ≤ VBB (a supply at VCC1.42 V, maximum output
amplitude) to VCC (minimum output amplitude). VBB is an externally
supplied voltage equal to VCC1.42 V (See Figures 2 and Figure 3). A
variable resistor between VCC and VBB, with the wiper driving
VCTRL, can control the output amplitude. Typical application circuits
and a VCTRL Voltage vs. Output Amplitude graph are described in this
data sheet. When left open, the VCTRL pin will be internally pulled
down to VEE and operate as a standard EP16, with 100% output
amplitude.
The VTT input pin offers an internal termination network for a 50 W
line impedance environment, shown in Figure 1. For further reference,
see Application Note AND8020, Termination of ECL Logic Devices.
Input considerations are required for D and D under no signal conditions
to prevent instability.
Special considerations are required for differential inputs under No
Signal conditions to prevent instability.
Features
220 ps Propagation Delay
Maximum Frequency > 4 GHz Typical (See Graph)
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 3.0 V to 5.5 V
Open Input Default State
50 W Internal Termination Resistor
PbFree Packages are Available
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
M
= Date Code
G
= PbFree Package
SOIC8
D SUFFIX
CASE 751
MARKING DIAGRAMS*
TSSOP8
DT SUFFIX
CASE 948R
ALYWG
G
KP63
1
8
1
8
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
1
8
KEP63
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506AA
3I
M
G
14
(Note: Microdot may be in either location)
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