参数资料
| 型号： | MC100EP196BMNR4G |
| 厂商： | ON Semiconductor |
| 文件页数： | 1/18页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 1024TAP 32-QFN |
| 标准包装： | 1 |
| 系列： | 100EP |
| 标片/步级数： | 1024 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 2.5ns |
| 接头增量： | 10ps |
| 可用的总延迟： | 2.5ns ~ 13ns |
| 独立延迟数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN（5x5） |
| 包装： | 剪切带 (CT) |
| 其它名称： | MC100EP196BMNR4GOSCT |
Semiconductor Components Industries, LLC, 2008
April, 2008 Rev. 1
1
Publication Order Number:
MC100EP196B/D
MC100EP196B
3.3 V ECL Programmable
Delay Chip With FTUNE
Descriptions
The MC100EP196B is a Programmable Delay Chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tunability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from VCC to VEE to fine tune the output delay from 0 to 60 ps.
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 3. The delay
increment of the EP196B has a digitally selectable resolution of about
10 ps and a net range of up to 10.4 ns. The required delay is selected by
the 10 data select inputs D[9:0] values and controlled by the LEN
(Pin 10). A LOW level on LEN allows a transparent LOAD mode of
real time delay values by D[9:0]. A LOW to HIGH transition on LEN
will LOCK and HOLD current values present against any subsequent
changes in D[10:0]. The approximate delay values for varying tap
numbers correlating to D0 (LSB) through D9 (MSB) are shown in
The IN/IN inputs can accept LVPECL (SE or Diff), or LVDS level
signals. Because the MC100EP196B is designed using a chain of
multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin
D10 is provided for controlling Pins 14 and 15, CASCADE and
CASCADE, also latched by LEN, in cascading multiple PDCs for
increased programmable range. The cascade logic allows full control of
multiple PDCs. Switching devices from all “1” states on D[0:9] with
SETMAX LOW to all “0” states on D[0:9] with SETMAX HIGH will
increase the delay equivalent to “D0”, the minimum increment.
Select input pins D[10:0] may be threshold controlled by
combinations of interconnects between VEF (pin 7) and VCF (pin 8) for
receiving LVCMOS, ECL, or LVTTL level signals. For LVCMOS input
levels, leave VCF and VEF open. For ECL operation, short VCF and VEF
(Pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to VCF and leave open VEF pin. The 1.5 V reference voltage at
the VCF pin can be accomplished by placing a 2.2 kW resistor between
VCF and VEE for a 3.3 V power supply.
The VBB pin, an internally generated voltage supply, is available to
this device only. For singleended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB and
VCC via a 0.01 mF capacitor and limit current sourcing or sinking to
0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
Maximum Input Clock Frequency >1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.2 ns to 12.4 ns
10 ps Increments
Linearity ±40 ps max
PECL Mode Operating Range:
VCC = 3.0 V to 3.6 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = 3.0 V to 3.6 V
IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels
A Logic High on the EN Pin Will Force Q to Logic Low
D[10:0] Can Select Either LVPECL, LVCMOS, or
LVTTL Input Levels
VBB Output Reference Voltage
These are PbFree Devices
MARKING
DIAGRAMS*
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
ORDERING INFORMATION
QFN32
MN SUFFIX
CASE 488AM
32
1
MC100
EP196B
ALYWG
1
32
1
MC100
EP196B
AWLYYWWG
LQFP32
FA SUFFIX
CASE 873A
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC100EP196FA | 功能描述:延迟线/计时元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| MC100EP196FAG | 功能描述:延迟线/计时元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| MC100EP196FAG | 制造商:ON Semiconductor 功能描述:Delay Line IC |
| MC100EP196FAR2 | 功能描述:延迟线/计时元素 3.3V/5V ECL RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| MC100EP196FAR2G | 功能描述:延迟线/计时元素 3.3V/5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
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