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参数资料
| 型号： | MC100EP221FA |
| 厂商： | MOTOROLA INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | LOW-VOLTAGE 1:20 DIFFERENTIAL ECL/PECL CLOCK DRIVER |
| 中文描述： | 100E SERIES, LOW SKEW CLOCK DRIVER, 20 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52 |
| 封装： | TQFP-52 |
| 文件页数： | 1/5页 |
| 文件大小： | 124K |
| 代理商： | MC100EP221FA |
SEMICONDUCTOR TECHNICAL DATA
1
REV 0.1
Motorola, Inc. 1997
2/97
The MC100EP221 is a low skew 1–to–20 differential driver, designed
with clock distribution in mind. It accepts two clock sources into an input
multiplexer. The input signals can be either differential or single–ended if
the VBB output is used. The selected signal is fanned out to 20 identical
differential outputs.
150ps Part–to–Part Skew
50ps Output–to–Output Skew
Differential Design
VBB Output
Voltage and Temperature Compensated Outputs
Low Voltage VEE Range of –2.375 to –3.8V
75k
Input Pulldown Resistors
The EP221 is specifically designed, modeled and produced with low
skew as the key goal. Optimal design and layout serve to minimize gate–
to–gate skew within a device, and empirical modeling is used to
determine process control limits that ensure consistent tpd distributions
from lot to lot. The net result is a dependable, guaranteed low skew
device.
To ensure that the tight skew specification is met it is necessary that
both sides of the differential output are terminated into 50
, even if only
one side is being used. In most applications, all ten differential pairs will
be used and therefore terminated. In the case where fewer than ten pairs
are used, it is necessary to terminate at least the output pairs on the same
package side as the pair(s) being used on that side, in order to maintain
minimum skew. Failure to do this will result in small degradations of
propagation delay (on the order of 10–20ps) of the output(s) being used
which, while not being catastrophic to most designs, will mean a loss of
skew margin.
The MC100EP221, as with most other ECL devices, can be operated from a positive VCC supply in PECL mode. This allows
the EP221 to be used for high performance clock distribution in +3.3V or +2.5V systems. Designers can take advantage of the
EP221’s performance to distribute low skew clocks across the backplane. In a PECL environment, series or Thevenin line
terminations are typically used as they require no additional power supplies. For more information on using PECL, designers
should refer to Motorola Application Note AN1406/D.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
LOW–VOLTAGE
1:20 DIFFERENTIAL
ECL/PECL CLOCK DRIVER
FA SUFFIX
52–LEAD TQFP PACKAGE
CASE 848D–03
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| MC100EP223 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Low-Voltage 1:22 Differential PECL/HSTL Clock Driver |
| MC100EP223TC | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:Low-Voltage 1:22 Differential PECL/HSTL Clock Driver |
| MC100EP24D | 制造商:ON Semiconductor 功能描述: |
| MC100EP29 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:3.3V / 5V ECL Dual Differential Data and Clock D Flip−Flop With Set and Reset |
| MC100EP29DT | 功能描述:触发器 3.3V/5V ECL Dual RoHS:否 制造商:Texas Instruments 电路数量:2 逻辑系列:SN74 逻辑类型:D-Type Flip-Flop 极性:Inverting, Non-Inverting 输入类型:CMOS 输出类型: 传播延迟时间:4.4 ns 高电平输出电流:- 16 mA 低电平输出电流:16 mA 电源电压-最大:5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:X2SON-8 封装:Reel |
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