参数资料
型号: MC100EP446FAG
厂商: ON Semiconductor
文件页数: 6/20页
文件大小: 0K
描述: IC CONV 8BIT SER/PAR ECL 32LQFP
标准包装: 250
应用: 数据管理
接口: 差分
电源电压: 3 V ~ 5.5 V
封装/外壳: 32-LQFP
供应商设备封装: 32-LQFP(7x7)
包装: 托盘
安装类型: 表面贴装
其它名称: MC100EP446FAGOS
MC10EP446, MC100EP446
http://onsemi.com
14
The device also features a differential SYNC input (Pins 29 and 30), which asynchronously reset all internal flip–flops and
clock circuitry on the rising edge of SYNC. The release of SYNC is a synchronous process, which ensures that no runt serial
data bits are generated. The falling edge of the SYNC followed by a falling edge of CLK initiates the start of the conversion
process on the next rising edge of CLK (Figures 9 and 10). As shown in the figures below, the device will start to latch the
parallel input data after the a falling edge of SYNC
, followed by the falling edge CLK , on the next rising of edge of CLK
for CKSEL LOW
Figure 9. Timing Diagram 1:8 Parallel to Serial Conversion with CKSEL LOW and SYNC
CLK
SYNC
SOUT
PCLK
D0
D02
D1
D2
D3
D4
D5
D6
D7
D22
D32
D42
D52
D62
D72
D03
D13
D23
D33
D43
D53
D63
D73
D12
CKSEL
D0
1
D1
1
D2
1
D3
1
D4
1
D5
1
D6
1
D7
1
D0
2
D1
2
D2
2
D3
2
D4
2
D6
2
D01
D21
D31
D41
D51
D61
D71
D11
D5
2
D04
D14
D24
D34
D44
D54
D64
D74
12
3
4
5
6
7
Data Latched
Figure 10. Synchronous Release of SYNC for CKSEL LOW
CLK
SYNC
(Asynchronous RESET)
SYNC
(Synchronous ENABLE)
Number of Clock Cycles from Data Latch to SOUT
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相关代理商/技术参数
参数描述
MC100EP446FAG 制造商:ON Semiconductor 功能描述:Translator / Logic Level Converter IC
MC100EP446FAR2 功能描述:串行到并行逻辑转换器 3.3V/5V ECL 8-Bit RoHS:否 制造商:Supertex 工作电源电压: 安装风格:SMD/SMT 封装 / 箱体:QFN-32 封装:Tray
MC100EP446FAR2G 功能描述:串行到并行逻辑转换器 3.3V/5V ECL 8-Bit Serial to Parallel RoHS:否 制造商:Supertex 工作电源电压: 安装风格:SMD/SMT 封装 / 箱体:QFN-32 封装:Tray
MC100EP446MNG 功能描述:串行到并行逻辑转换器 ECL PARA T/SERIAL RoHS:否 制造商:Supertex 工作电源电压: 安装风格:SMD/SMT 封装 / 箱体:QFN-32 封装:Tray
MC100EP446MNR4G 功能描述:串行到并行逻辑转换器 ECL PARA T/SERIAL RoHS:否 制造商:Supertex 工作电源电压: 安装风格:SMD/SMT 封装 / 箱体:QFN-32 封装:Tray