参数资料
型号: MC100ES6014DWR2
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 时钟及定时
英文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20
封装: PLASTIC, SOIC-20
文件页数: 1/6页
文件大小: 291K
代理商: MC100ES6014DWR2
7
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order Number: MC100ES6014/D
Rev 0, 05/2003
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
665
Preliminary Information
2.5V / 3.3V1:5 Differential
ECL/PECL/HSTL/LVDS Clock
Driver
The MC100ES6014 is a low skew 1–to–5 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The ECL/PECL input signals can be either differential or
single–ended (if the VBB output is used). HSTL and LVDS inputs can be
used when the ES6014 is operating under PECL conditions.
The ES6014 specifically guarantees low output–to–output skew. Opti-
mal design, layout, and processing minimize skew within a device and
from device to device.
To ensure that the tight skew specification is realized, both sides of any
differential output need to be terminated identically into 50
W even if only
one output is being used. If an output pair is unused, both outputs may be
left open (unterminated) without affecting skew.
The common enable (EN) is synchronous, outputs are enabled/ dis-
abled in the LOW state. This avoids a runt clock pulse when the device is
enabled/disabled as can happen with an asynchronous control. The inter-
nal flip flop is clocked on the falling edge of the input clock; therefore, all
associated specification limits are referenced to the negative edge of the
clock input.
The MC100ES6014, as with most other ECL devices, can be operated
from a positive VCC supply in PECL mode. This allows the ES6014 to be
used for high performance clock distribution in +3.3 V or +2.5 V systems.
Single ended CLK input pin operation is limited to a VCC ≥ 3.0 V in PECL
mode, or VEE ≤ –3.0 V in ECL mode. Designers can take advantage of the
ES6014’s performance to distribute low skew clocks across the back-
plane or the board.
Features
100 ps Device–to–Device Skew
25 ps Within Device Skew
400 ps Typical Propagation Delay
Maximum Frequency > 2 GHz Typical
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode: VCC = 2.375 V to 3.8 V
with VEE = 0 V
ECL Mode: VCC = 0 V
with VEE = –2.375 V to –3.8 V
LVDS and HSTL Input Compatible
Open Input Default State
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
MC100ES6014
DT SUFFIX
20 LEAD TSSOP PACKAGE
CASE 948E
DW SUFFIX
20 LEAD SOIC PACKAGE
CASE 751D
Device
Package
ORDERING INFORMATION
MC100ES6014DT
TSSOP–20
MC100ES6014DTR2
TSSOP–20
MC100ES6014DW
SO–20
MC100ES6014DWR2
SO–20
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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