参数资料
型号: MC100ES6220AER2
厂商: IDT, Integrated Device Technology Inc
文件页数: 4/9页
文件大小: 0K
描述: IC CLK BUFFER 1:10 1GHZ 52-LQFP
标准包装: 1,500
系列: 100ES
类型: 扇出缓冲器(分配)
电路数: 2
比率 - 输入:输出: 1:10
差分 - 输入:输出: 是/是
输入: ECL,PECL
输出: LVPECL
频率 - 最大: 1GHz
电源电压: 2.375 V ~ 3.465 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 52-LQFP 裸露焊盘
供应商设备封装: 52-PTQFP(10x10)
包装: 带卷 (TR)
Advanced Clock Drivers Devices
4
Freescale Semiconductor
MC100ES6220
Table 4. PECL DC Characteristics (VCC = 2.5 V ± 5% or VCC = 3.3 V ± 5%, VEE = GND, TJ = 0°C to +110°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL differential signals)
VPP
Differential Input Voltage(1)
1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
0.1
1.3
V
Differential operation
VCMR
Differential Cross Point Voltage(2)
2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
1.0
VCC – 0.3
V
Differential operation
IIN
Input Current(1)
±150
AVIN = VIL or VIN = VIH
Clock Inputs (PECL single ended signals)
VIH
Input Voltage High
VCC – 1.165
VCC – 0.880
V
VIL
Input Voltage Low
VCC – 1.810
VCC – 1.475
V
IIN
Input Current(3)
3. Input have internal pullup/pulldown resistors which affect the input current.
±150
AVIN = VIL or VIN = VIH
PECL Clock Outputs (QA0-A9, QA0-A9, QB0-B9, QB0-B9)
VOH
Output High Voltage
VCC – 1.1
VCC – 1.005
VCC – 0.7
V
IOH = –30 mA(4)
4. Termination 50
to VTT.
VOL
Output Low Voltage
VCC – 1.9
VCC – 1.705
VCC – 1.4
V
IOL = –5 mA(4)
Supply current and VBB
IEE(5)
5. ICC calculation:
ICC = (number of differential output used) x (IOH + IOL) + IEE
ICC = (number of differential output used) x (VOH – VTT) ÷ Rload + (VOL – V TT) ÷Rload + IEE.
Maximum Quiescent Supply Current without
Output Termination Current
80
130
mA
VEE pins
VBB
Output Reference Voltage
VCC – 1.42
VCC – 1.20
V
IBB = 0.3 mA
Table 5. ECL DC Characteristics (VEE = –2.5 V ± 5% or VEE = –3.3 V ± 5%, VCC = GND, TJ = 0°C to +110°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (ECL differential signals)
VPP
Differential Input Voltage(1)
1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality.
0.1
1.3
V
Differential operation
VCMR
Differential Cross Point Voltage(2)
2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC)
range and the input swing lies within the VPP (DC) specification.
VEE + 1.0
–0.3
V
Differential operation
IIN
Input Current(1)
±150
AVIN = VIL or VIN = VIH
Clock Inputs (ECL single ended signals)
VIH
Input Voltage High
–1.165
–0.880
V
VIL
Input Voltage Low
–1.810
–1.475
V
IIN
Input Current(3)
3. Input have internal pullup/pulldown resistors which affect the input current.
±150
AVIN = VIL or VIN = VIH
ECL Clock Outputs (QA0–A9, QA0–A9, QB0–B9, QB0–B9)
VOH
Output High Voltage
–1.1
–1.005
–0.7
V
IOH = –30 mA(4)
4. Termination 50
to VTT.
VOL
Output Low Voltage
–1.9
–1.705
–1.4
V
IOL = –5 mA(4)
Supply Current and VBB
IEE(5)
5. ICC calculation: ICC = (number of differential output used) x (IOH + IOL) + IEE
ICC = (number of differential output used) x (VOH – VTT) ÷ Rload + (VOL – V TT) ÷ Rload + IEE.
Maximum Quiescent Supply Current without
Output Termination Current
80
130
mA
VEE pins
VBB
Output Reference Voltage
–1.42
–1.20
V
IBB = 0.3 mA
MC100ES6220
Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
NETCOM
IDT Low Voltage Dual 1:10 Differential ECL/PECL Clock Fanout Buffer
Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc
MC100ES6220
4
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