参数资料
型号: MC100ES8111FAR2
厂商: MOTOROLA INC
元件分类: 时钟及定时
英文描述: 100E SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32
封装: 7 X 7 MM, PLASTIC, LQFP-32
文件页数: 5/6页
文件大小: 117K
代理商: MC100ES8111FAR2
7
MC100ES8111
MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA
745
Table 6. AC Characteristics (VCC = 3.3V±5%, VCCO = 1.5V±0.1V or VCCO = 1.8V±0.1V, TJ = 0°C to + 110°C) a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock input pair CLK0, CLK0 (HSTL differential signals)
VDIF
Differential input voltagec (peak-to-peak)
0.4
V
VX, IN
Differential cross point voltaged
0.68
0.9
V
fCLK
Input Frequency
0-400
TBD
MHz
tPD
Propagation Delay CLK0 to Q[0-9]
TBD
ps
Clock input pair CLK1, CLK1 (PECL differential signals)
VPP
Differential input voltagee (peak-to-peak)
0.2
1.0
V
VCMR
Differential input crosspoint voltagef
1
VCC-0.6
V
fCLK
Input Frequency
0-400
MHz
Differential
tPD
Propagation Delay CLK1 to Q[0-9]
TBD
ps
Differential
HSTL clock outputs (Q[0-9], Q[0-9])
VX, OUT
Output differential crosspoint
0.68
0.75
0.9
V
VOH
Output High Voltage
1
V
VOL
Output Low Voltage
0.5
V
VO(P-P)
Differential output voltage (peak-to-peak)
0.5
V
tsk(O)
Output-to-output skew
50
ps
Differential
tsk(PP)
Output-to-output skew (part-to-part)
TBD
ps
Differential
tJIT(CC)
Output cycle-to-cycle jitter
TBD
DCO
Output duty cycle
TBD
50
TBD
%
DCfref= 50%
tr, tf
Output Rise/Fall Time
0.05
TBD
ns
20% to 80%
tPDLg
Output disable time
2.5
T + tPD
3.5
T + tPD
ns
T=CLK period
tPLDh
Output enable time
3
T + tPD
4
T + tPD
ns
T=CLK period
a. AC characteristics are design targets and pending characterization.
b. AC characteristics apply for parallel output termination of 50
to VTT.
c. VDIF (DC) is the minimum differential HSTL input voltage swing required for device functionality.
d. VX (DC) is the crosspoint of the differential HSTL input signal. Functional operation is obtained when the crosspoint is within the VX (DC)
range and the input swing lies within the VDIF (DC) specification.
e. VPP (AC) is the minimum differential PECL input voltage swing required to maintain AC characteristics including tpd and device-to-device
skew.
f.
VCMR (AC) is the crosspoint of the differential HSTL input signal. Normal AC operation is obtained when the crosspoint is within the VCMR
(AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device propagation
delay, device and part-to-part skew.
g. Propagation delay OE deassertion to differential output disabled (differential low: true output low, complementary output high).
h. Propagation delay OE assertion to output enabled (active).
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