参数资料
| 型号： | MC100LVEL32DT |
| 厂商： | ON Semiconductor |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | IC DIVIDER DIV X2 ECL DFF 8TSSOP |
| 产品变化通告： | LTB Notification 03/Jan/2008 |
| 标准包装： | 100 |
| 系列： | 100LVEL |
| 逻辑类型： | 除以 2 |
| 元件数： | 1 |
| 每个元件的位元数： | 1 |
| 复位： | 异步 |
| 计数速率： | 2.6GHz |
| 触发器类型： | 正，负 |
| 电源电压： | 3 V ~ 3.8 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
| 其它名称： | MC100LVEL32DTOS |
MC100LVEL32
http://onsemi.com
2
4
3
Figure 1. Logic Diagram and Pinout Assessment
1
2
5
6
7
8
Q
VEE
VCC
Q
CLK
VBB
R
÷2
Reset
CLK
Table 1. PIN DESCRIPTION
Pin
Function
CLK*, CLK**
Q, Q
Reset*
VBB
VCC
VEE
EP
ECL Differential Clock Inputs
ECL Differential Data ÷2 Outputs
ECL Asynch Reset
Reference Voltage Output
Positive Supply
Negative Supply
(DFN8 only) Thermal exposed pad
must be connected to a sufficient
thermal conduit. Electrically connect to
the most negative supply (GND) or
leave unconnected, floating open.
*Pin will default low when left open, per internal 75 K pulldown to
VEE.
** Pin will default to VCC/2 when left open per internal 75 KW pull-
down to VEE and 75 KW pullup to VCC.
Table 2. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI v VCC
VI w VEE
6 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
VI v VCC
VI w VEE
6 to 0
V
Iout
Output Current
Continuous
Surge
50
100
mA
IBB
VBB Sink/Source
± 0.5
mA
TA
Operating Temperature Range
40 to +85
°C
Tstg
Storage Temperature Range
65 to +150
°C
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
SOIC8
190
130
°C/W
qJC
Thermal Resistance (JunctiontoCase)
Standard Board
SOIC8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
TSSOP8
185
140
°C/W
qJC
Thermal Resistance (JunctiontoCase)
Standard Board
TSSOP8
41 to 44 ± 5%
°C/W
qJA
Thermal Resistance (JunctiontoAmbient)
0 lfpm
500 lfpm
DFN8
129
84
°C/W
Tsol
Wave Solder
Pb
PbFree
<2 to 3 sec @ 248°C
<2 to 3 sec @ 260°C
265
°C
qJC
Thermal Resistance (JunctiontoCase)
(Note 1)
DFN8
35 to 40
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. JEDEC standard multilayer board 2S2P (2 signal, 2 power)
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