参数资料
型号: MC10137L
厂商: MOTOROLA INC
元件分类: 通用总线功能
英文描述: Replaced by CD54HCT191 : Synchronous Up/Down Counters With Down/Up Mode Control 16-CDIP -55 to 125
中文描述: 10K SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT BIDIRECTIONAL DECADE COUNTER, CDIP16
封装: CERAMIC, DIP-16
文件页数: 3/6页
文件大小: 127K
代理商: MC10137L
MC10137
3–37
MOTOROLA
MECL Data
DL122 — Rev 6
ELECTRICAL CHARACTERISTICS
Pin
Under
Test
Test Limits
–30
°
C
+25
°
C
+85
°
C
Characteristic
Symbol
Min
Max
Min
Typ
Max
Min
Max
Unit
Power Supply Drain Current
IE
IinH
8
165
120
150
165
mAdc
Input Current
5,6,11,12
7
9,10
13
350
425
390
460
220
265
245
290
220
265
245
290
μ
Adc
IinL
VOH
VOL
VOHA
VOLA
All
0.5
0.5
0.3
μ
Adc
Output Voltage
Logic 1
14
(
2.
)
–1.060
–0.890
–0.960
–0.810
–0.890
–0.700
Vdc
Output Voltage
Logic 0
14
(
2.
)
–1.890
–1.675
–1.850
–1.650
–1.825
–1.615
Vdc
Threshold Voltage
Logic 1
14
(
2.
)
–1.080
–0.980
–0.910
Vdc
Threshold Voltage
Logic 0
14
(
2.
)
–1.655
–1.630
–1.595
Vdc
Switching Times
(50
Load)
ns
Propagation Delay
Clock Input
t13+14+
t13+14–
t13+4+
t13+4–
t10–4–
t10+4+
t12+13+
t12–13+
t9+13+
t7+13+
t10–13+
t13+10+
t13+12+
t13+12–
t13+9+
t13+7+
t13+10–
t10+13+
fcountup
fcountdown
t4+
t14+
t4–
t14–
14
14
4
4
0.8
0.8
2.0
2.0
4.8
4.8
10.9
10.9
1.0
1.0
2.5
2.5
3.3
3.3
7.0
7.0
4.5
4.5
10.5
10.5
1.1
1.1
2.4
2.4
5.0
5.0
11.5
11.5
Carry In to Carry Out
4
(
3.
)
4
1.6
1.6
7.4
7.4
1.6
1.6
5.0
5.0
6.9
6.9
1.9
1.9
7.5
7.5
Setup Time
Data Inputs
14
14
3.5
3.5
3.5
3.5
3.5
3.5
Select Inputs
14
14
7.5
7.5
7.5
7.5
7.5
7.5
Carry In Input
14
14
4.5
–1.0
3.7
–1.0
4.5
–1.0
Hold Time
Data Inputs
14
14
0
0
0
0
0
0
Select Inputs
14
14
–2.5
–2.5
–2.5
–2.5
–2.5
–2.5
Carry In Input
14
14
–1.6
4.0
–1.6
3.1
–1.6
4.0
Counting Frequency
14
14
125
125
125
125
150
150
125
125
MHz
Rise Time
(20 to 80%)
4
14
0.9
0.9
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
ns
Fall Time
(20 to 80%)
4
14
0.9
0.9
3.3
3.3
1.1
1.1
2.0
2.0
3.3
3.3
1.1
1.1
3.5
3.5
1. Individually apply VILmin to pin under test.
2. Measure output after clock pulse
VIH
VIL
appears at clock input (Pin 13).
3. Before test set Q1 and Q2 outputs to a logic low.
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