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参数资料
| 型号： | MC10175FN |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | 锁存器 |
| 英文描述： | 10K SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PQCC20 |
| 封装： | PLASTIC, LCC-20 |
| 文件页数： | 3/8页 |
| 文件大小： | 106K |
| 代理商： | MC10175FN |
MC10175
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (continued)
TEST VOLTAGE VALUES (Volts)
@ Test Temperature
VIHmax
VILmin
VIHAmin
VILAmax
VEE
–30
°C
–0.890
–1.890
–1.205
–1.500
–5.2
+25
°C
–0.810
–1.850
–1.105
–1.475
–5.2
+85
°C
–0.700
–1.825
–1.035
–1.440
–5.2
Pin
Under
TEST VOLTAGE APPLIED TO PINS LISTED BELOW
(V
)
Characteristic
Symbol
Under
Test
VIHmax
VILmin
VIHAmin
VILAmax
VEE
(VCC)
Gnd
Power Supply Drain Current
IE
8
1, 16
Input Current
IinH
6
7
10
11
6
7
10
11
8
1, 16
IinL
All
Note 1.
8
1, 16
Output Voltage
Logic 1
VOH
14
15
10
12
6
8
1, 16
Output Voltage
Logic 0
VOL
14
15
6, 10
6, 12
8
1, 16
Threshold Voltage
Logic 1
VOHA
14
15
6
10
12
8
1, 16
Threshold Voltage
Logic 0
VOLA
14
15
6
10
12
8
1, 16
Switching Times
(50
Load)
+1.11V
+0.31V
Pulse In
Pulse Out
–3.2 V
+2.0 V
Data Input
t10+14+
t10–14–
14
6, 7
10
14
8
1, 16
Clock Input
t6–14+
t6–14–
14
7
10, 6
14
8
1, 16
Reset Input
t11+4–
t11+14–
4
14
5
10
6
7, 11
4 (2.)
14 (2.)
8
1, 16
Setup TIme
Hold Time
tsetup
thold
14
7
6, 10
14
8
1, 16
Rise Time
(20 to 80%)
t+
14
6, 7
10
14
8
1, 16
Fall Time
(20 to 80%)
t–
14
6, 7
10
14
8
1, 16
1. Individually test each input; apply VILmin to pin under test.
2. Output latched to high logic state prior to test.
Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been
established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained.
Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the
same manner.
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