参数资料
| 型号： | MC10E196FNG |
| 厂商： | ON Semiconductor |
| 文件页数： | 1/12页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 128TAP 28-PLCC |
| 产品变化通告： | Dimensional change 21/Oct/2008 |
| 标准包装： | 37 |
| 系列： | 10E |
| 标片/步级数： | 128 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 1.39ns |
| 接头增量： | 20ps |
| 可用的总延迟： | 1.39ns ~ 3.63ns |
| 独立延迟数： | 1 |
| 电源电压： | 4.2 V ~ 5.7 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-LCC（J 形引线） |
| 供应商设备封装： | 28-PLCC（11.51x11.51） |
| 包装： | 管件 |
Semiconductor Components Industries, LLC, 2006
November, 2006 Rev. 9
1
Publication Order Number:
MC10E196/D
MC10E196, MC100E196
5VECL Programmable
Delay Chip
Description
The MC10E/100E196 is a programmable delay chip (PDC)
designed primarily for very accurate differential ECL input edge
placement applications.
The delay section consists of a chain of gates and a linear ramp delay
adjust organized as shown in the logic symbol. The first two delay
elements feature gates that have been modified to have delays
1.25 and 1.5 times the basic gate delay of approximately 80 ps. These
two elements provide the E196 with a digitally-selectable resolution
of approximately 20 ps. The required device delay is selected by the
seven address inputs D[0:6], which are latched on chip by a high signal
on the latch enable (LEN) control.
The FTUNE input takes an analog voltage and applies it to an
internal linear ramp for reducing the 20 ps Least Significant Bit (LSB)
minimum resolution still further. The FTUNE input is what
differentiates the E196 from the E195.
An eighth latched input, D7, is provided for cascading multiple
PDC’s for increased programmable range. The cascade logic allows
full control of multiple PDC’s, at the expense of only a single added
line to the data bus for each additional PDC, without the need for any
external gating.
The VBB pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to VBB as a switching reference voltage.
VBB may also rebias AC coupled inputs. When used, decouple VBB
and VCC via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, VBB should be left open.
The 100 Series contains temperature compensation.
Features
2.0 ns Worst Case Delay Range
≈20 ps/Delay Step Resolution
Linear Input for Tighter Resolution
>1.0 GHz Bandwidth
On Chip Cascade Circuitry
PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V
with VEE = 4.2 V to 5.7 V
Internal Input 50 kW Pulldown Resistors
ESD Protection: Human Body Model; > 1 kV,
Machine Model; > 75 V
Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
Moisture Sensitivity Level: Pb = 1; PbFree = 3
For Additional Information, see Application Note
AND8003/D
Flammability Rating: UL 94 V0 @ 1.125 in,
Oxygen Index: 28 to 34
Transistor Count = 425 devices
PbFree Packages are Available*
*For additional information on our PbFree strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
MARKING DIAGRAM*
xxx
= 10 or 100
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
PLCC28
FN SUFFIX
CASE 776
MCxxxE196FNG
AWLYYWW
1
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
ORDERING INFORMATION
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MC10E196FNR2 | 功能描述:延迟线/计时元素 5V ECL Programmable RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| MC10E196FNR2G | 功能描述:延迟线/计时元素 5V ECL Programmable Delay RoHS:否 制造商:Micrel 功能:Active Programmable Delay Line 传播延迟时间:1000 ps 工作温度范围: 封装 / 箱体:QFN-24 封装:Tube |
| MC10E197FN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC10E211 C14N WAF | 制造商:ON Semiconductor 功能描述: |
| MC10E211FN | 功能描述:时钟驱动器及分配 5V ECL 1:6 Diff RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
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